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preliminary publication# 22304 rev: c amendment/ 0 issue date: july 2000 re f er to amd?s website ( www.amd.com ) f or the latest in f ormation. AM79C901A homephy? single-chip 1/10 mbps home networking phy distinctive characteristics fully integrated 1 mbps homepna physical layer (phy) as defined by home phoneline networking alliance (homepna) specification 1.1 ? optimized for home networking applications over existing telephone wire ? media independent interface (mii)-compatible for connecting external media access controller (mac) ? in-band control features: adjustable power and speed levels 32 bits of reserved in-band messaging piggy- backed on ethernet packet ? register programmable features: power control speed control performance registers optional control of squelch algorithm major frame timing parameters programma- ble: isbi, aid isbi, pulse width, inter-symbol time ? any1home ? link detection: indicates to the mac that a valid home net- working node has been detected detects a network failure and allows the upper layer protocol to take corrective action fully integrated 10 mbps ethernet transceiver ? comprehensive auto-negotiation implementation ? ieee 802.3u-compliant mii ? full-duplex operation supported on the mii port with independent transmit (tx) and receive (rx) channels ? optimized for 10base-t applications compliant with homepna specification 1.1 general purpose serial interface (gpsi)/serial peripheral interface (spi) extensive programmable internal/external loopback capabilities extensive led status support ieee 1149.1-compliant jtag boundary scan test access port interface very low power consumption +3.3 v power supply along with 5 v tolerant i/os enable broad system compatibility ? xtal1 supports 3.3 v i/o only ? xtal2 supports 1.0 v i/o only available in 68-pin plcc and 80-pin tqfp packages industrial temperature support (-40 o c to +85 o c) general description the AM79C901A homephy is a single-chip device that contains both a physical layer (phy) for 1 mbps data networking over existing residential telephone wiring based on the specification published by homepna and a physical layer for supporting the ieee 802.3 standard for 10base-t. the homephy is targeted at embedded applications and has both gpsi and mii-compatible interfaces. the integrated homepna transceiver is a physical layer device that enables data networking at speeds up to 1 mbps over existing residential phone wiring regardless of topology and without disrupting telephone (pots) service. the integrated ethernet transceiver is a physical layer device supporting the ieee 802.3 standard for 10base-t. it provides all of the phy layer functions required to support 10 mbps data transfer speeds. a compliant ieee 1149.1 jtag test interface for board level testing is provided. the AM79C901A phy also provides on-chip led drivers for collision, link integrity, speed, activity, and power output. the AM79C901A phy is fabricated in an advanced low power 3.3 v cmos process to provide low operating current for power sensitive applications. the AM79C901A phy is available in the commercial temperature range (0oc to +70oc) in 68-pin plcc and 80-pin tqfp packages. the AM79C901A also supports the industrial temperature range (-40oc to +85oc) in the 80-pin tqfp package. the industrial temperature range is well suited to environments with enclosures with restricted air flow or outdoor equipment.
2 AM79C901A preliminary block diagram mii/gpsi interface col act link speed hrtxrxp/n phy_sel phy_ad isolate mii/gpsi gm_mode rxdat, rxclk, rxcrs, cls, txdat, txclk, txen or rxd[3:0], txd[3:0], crs, col, rx_dv, tx_en, tx_clk, rx_clk, rx_er mdc, mdio or sclk, sdi, sdo, cs power tdo tdi tclk tms led interface jtag port control link control data interface drive control analog front end transmit state machine receive state machine phy control & registers link control data interface transmit state machine receive state machine phy control & registers clock reference data control 10base-t phy 1mbps homepna phy tx rx xtal1 xtal2 xclk/xtal control data control 22304b-1
AM79C901A 3 preliminary table of contents AM79C901A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 connection diagram (pl 068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 connection diagram (pqt 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin designations (pl 068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pin designations (pqt 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 listed by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pin designations (pl 068) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 listed by group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pin designations (pqt 80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 listed by group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 listed by driver type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 standard products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 board interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 gpsi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 spi interface (slave mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ieee 1149.1 (jtag) test access port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ethernet network interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 homepna phy network interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 clock interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 basic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 network interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 phy data interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 h_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 s_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 detailed functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 gpsi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 serial peripheral interface (spi-slave) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 mii-compatible interface for homepna phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 mii-compliant interface for 10base-t phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1 mbps homepna phy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 homepna phy medium interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 homepna phy symbol waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 time interval unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 jam signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 access id values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 silence interval (aid symbol 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 data symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 mode interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1 mbps homepna phy loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 any1home link detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10base-t phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 twisted pair transmit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 twisted pair receive function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 twisted pair interface status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 collision detect function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 jabber function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 AM79C901A preliminary reverse polarity detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 soft reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10base-t loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 led support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ieee 1149.1 (jtag) test access port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 boundary scan circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 tap finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 supported instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 instruction register and decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 other data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 boundary scan cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 user accessible registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1 mbps homepna phy management registers (hprs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 hpr0: homepna phy control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 hpr1: homepna phy status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 hpr2 and hpr3: homepna phy id registers (registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 hpr4: homepna phy auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . . . . . . 47 hpr5: homepna phy auto-negotiation link partner ability register (register 5). . . . . . . . . . . . . . . . . 48 hpr6: homepna phy auto-negotiation expansion register (register 6) . . . . . . . . . . . . . . . . . . . . . . . 49 hpr7: homepna phy auto-negotiation next page register (register 7) . . . . . . . . . . . . . . . . . . . . . . . 49 reserved registers: hpr8 - hpr15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 hpr16: homepna phy control register (register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 hpr17: homepna phy status/control register (register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 hpr18 and hpr19: homepna phy txcomm registers (registers 18 and 19) . . . . . . . . . . . . . . . . . . 51 hpr20 and hpr21: homepna phy rxcomm registers (registers 20 and 21) . . . . . . . . . . . . . . . . . . 52 hpr22: homepna phy aid register (register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 hpr23: homepna phy noise control register (register 23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 hpr24: homepna phy noise control 2 register (register 24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 hpr25: homepna phy noise statistics register (register 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 hpr26: homepna phy event status register (register 26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 hpr27: homepna phy aid control register (register 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 hpr28: homepna phy isbi control register (register 28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 hpr29: homepna phy tx control register (register 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 hpr30: homepna phy drive level control register (register 30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 hpr31: homepna phy analog control register (register 31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10base-t phy management registers (tbrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 tbr0: 10base-t phy control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 tbr1: 10base-t status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 tbr2 and tbr3: 10base-t phy identifier register (registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . 59 tbr4: 10base-t auto-negotiation advertisement register (register 4) . . . . . . . . . . . . . . . . . . . . . . . . 60 tbr5: 10base-t auto-negotiation link partner ability register (register 5) . . . . . . . . . . . . . . . . . . . . . 61 tbr6: 10base-t auto-negotiation expansion register (register 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 tbr7: 10base-t auto-negotiation next page register (register 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 reserved registers (registers 8-15, 18, 20-23, and 25-31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 tbr16: 10base-t status and enable register (register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 tbr17: 10base-t phy control/status register (register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 tbr19: 10base-t phy management extension register (register 19) . . . . . . . . . . . . . . . . . . . . . . . . 65 tbr24: 10base-t summary status register (register 24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 switching test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 gpsi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10base-t transmit timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10base-t receive timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10base-t transmit clock timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10base-t receive clock timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 1 mbps homepna transmit timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
AM79C901A 5 preliminary 1 mbps homepna receive timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1 mbps homepna clock timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10base-t transmit timing (mii). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10base-t receive timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10base-t transmit clock timing (mii). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10base-t receive clock timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1 mbps homepna transmit timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1 mbps homepna receive timing (mii). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1 mbps homepna clock timing (mii). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 mdc/mdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10base-t pmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1 mbps homepna analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 external clock (xtal1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 physical dimensions*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 pl 068 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 pqt 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6 AM79C901A preliminary list of figures figure 1. idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 2. rxpkt - rxcrs asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 3. rxpkt - rxcrs cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. txpkt - txen asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. txpkt - rxclk active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. txpkt - txen cleared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. txpkt - cls asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 8. rxpkt - cls asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 9. operation of the spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 10. spi read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 11. aborted operation of the spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 12. first operation following an abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13. normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 14. mii start of transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15. mii end of transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16. homepna phy framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 17. aid symbol transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 18. aid symbol receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 19. transmit data symbol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 20. receive symbol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 21. rll 25 coding tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 22. 10base-t transmit and receive data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 23. normal and tri-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 9 figure 24. 10 mbps transmit timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 25. 10 mbps receive start of packet timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 26. 10 mbps receive end of packet timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 27. 10 mbps transmit and receive clock timing (gpsi). . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 28. 1 mbps homepna transmit timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 29. 1 mbps homepna receive timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 30. 1 mbps homepna clock timing (gpsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 31. 10 mbps transmit timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 32. 10 mbps receive start of packet timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 33. 10 mbps receive end of packet timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 34. 10 mbps transmit and receive clock timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 35. 1 mbps homepna transmit timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 36. 1 mbps homepna receive timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 37. 1 mbps homepna clock timing (mii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 38. mii management timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 39. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 figure 40. 10 mbps transmit (tx) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 41. 10 mbps receive (rx) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 42. homepna phy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 43. jtag (ieee 1149.1) test signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 44. external clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
AM79C901A 7 preliminary list of tables table 1. clock source selection 21 table 2. gpsi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 3. spi op codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 4. mii-compatible timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 5. mii control frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 6. homepna phy pulse parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 7. access id symbol pulse positions and encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 8. blanking interval speed settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 table 9. master station control word functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 10. auto-negotiation capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 11. led default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 12. ieee 1149.1 supported instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 13. bsr mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 15. boundary scan ring order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1 table 16. 1 mbps homepna phy management registers (hprs) . . . . . . . . . . . . . . . . . . . . . . .43 table 17. hpr0: homepna phy control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 18. hpr1: homepna phy status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 19. hpr2: homepna phy id register (register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 20. hpr3: homepna phy id register (register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 21. hpr4: homepna phy auto-negotiation advertisement register (register 4) . . . . . .47 table 22. hpr5: homepna phy auto-negotiation link partner ability register - base page format (register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 23. hpr5: homepna phy auto-negotiation link partner ability register - next page format (register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8 table 24. hpr6: homepna phy auto-negotiation expansion register (register 6) . . . . . . . . .49 table 25. hpr7: homepna phy auto-negotiation next page register (register 7) . . . . . . . . .49 table 26. hpr16: homepna phy control register (register 16) . . . . . . . . . . . . . . . . . . . . . . . .50 table 27. hpr17: homepna phy status/control register (register 17) . . . . . . . . . . . . . . . . . .51 table 28. hpr18 and hpr19: homepna phy txcomm registers (registers 18 and 19) . . . .52 table 29. hpr20 and hpr21: homepna phy rxcomm registers (registers 20 and 21) . . . .52 table 30. hpr22: homepna phy aid register (register 22) . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 31. hpr23: homepna phy noise control register (register 23) . . . . . . . . . . . . . . . . . . 53 table 32. hpr24: homepna phy noise control 2 register (register 24) . . . . . . . . . . . . . . . . .53 table 33. hpr25: homepna phy noise statistics register (register 25) . . . . . . . . . . . . . . . . .54 table 34. hpr26: homepna phy event status register (register 26) . . . . . . . . . . . . . . . . . . .54 table 35. hpr27: homepna phy aid control register (register 27) . . . . . . . . . . . . . . . . . . . .55 table 36. hpr28: homepna phy isbi control register (register 28) . . . . . . . . . . . . . . . . . . . 55 table 37. hpr29: homepna phy tx control register (register 29) . . . . . . . . . . . . . . . . . . . . .55 table 38. hpr30: homepna phy drive level control register (register 30) . . . . . . . . . . . . . .56 table 39. hpr31: homepna phy analog control register (register 31) . . . . . . . . . . . . . . . . .56 table 40. 10base-t phy management registers (tbrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 41. tbr0: 10base-t phy control register (register 0) . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 42. tbr1: 10base-t phy status register (register 1) . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 43. tbr2: 10base-t phy identifier register (register 2) . . . . . . . . . . . . . . . . . . . . . . . . .60 table 44. tbr3: 10base-t phy identifier register (register 3) . . . . . . . . . . . . . . . . . . . . . . . . .60 table 45. tbr4: 10base-t auto-negotiation advertisement register (register 4) . . . . . . . . . . 61 table 46. tbr5: 10base-t auto-negotiation link partner ability register (register 5) - base page format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 47. tbr5: 10base-t auto-negotiation link partner ability register (register 5) - next page format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 48. tbr6: 10base-t auto-negotiation expansion register (register 6) . . . . . . . . . . . . . .63 table 49. tbr7: 10base-t auto-negotiation next page register (register 7) . . . . . . . . . . . . . .63 table 50. tbr16: 10base-t status and enable register (register 16). . . . . . . . . . . . . . . . . . . 64 table 51. tbr17: 10base-t phy control/status register (register 17) . . . . . . . . . . . . . . . . . 65 table 52. tbr19: 10base-t phy management extension register (register 19) . . . . . . . . . . .66 table 53. tbr24: 10base-t summary status register (register 24) . . . . . . . . . . . . . . . . . . . .66
8 AM79C901A preliminary connection diagram (pl 068) note : nc pins are reserved and should be left unconnected. 4 321 8765 9 6867666564636261 13 14 12 11 10 15 16 17 18 19 20 21 22 23 24 25 26 32 33 34 35 28 29 30 31 27 36 37 38 39 40 41 42 43 57 56 58 59 60 55 54 53 52 51 50 49 48 47 46 45 44 rx_dv dvdd dvss rxd0/rxdat rxd1 rx_clk/rxclk avdd phy_sel dvdd rx_er dvss gm_mode tx_clk/txclk tx_en/txen txd0/txdat txd1/sdi nc nc rx- avdd rx+ avss tx- avdd tx+ avss iref avdd hrtxrxp avdd hrtxrxn avss avss avdd rxd2 rxd3 dvss led_speed led_power dvdd led_activity led_col led_link mdc/sclk dvss mdio/sdo isolate phy_ad mii/gpsi ten reset col/cls dvss dvss txd3/cs txd2 crs/rxcrs dvdd dvdd tdo tck tms tdi xclk/xtal xtal2 xtal1 avdd nc am79c901 homephy 22304b-2 a
AM79C901A 9 preliminary connection diagram (pqt 80) 22304b- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc nc rx01 rxd0/rxoat dvss rx_dv dvdd rx_clk/rxclk avdd phy_sel dvdd rx_er dvss gm_mode tx_clk/txclk tx_en/txen txd0/txdat txd1/sdi nc nc nc nc txd2 txd3/cs dvss col/cls dvss crs/rxcrs dvdd dvdd tdo tdk tms tdi xclk/xtal xtal2 xtal1 avdd nc nc nc nc reset ten mh/gpsi phy_ad isolate mdio/sdo dvss mdc/sclk led_link led_col led_activity dvdd led_power led_speed dvss rxd3 rxd2 nc nc nc rx- avdd rx+ avss tx- avdd tx+ avss iref avdd hrtxrxp avdd hrtxrxn avss avss avdd nc nc am79c901 a homephy note : nc pins are reserved and should be left unconnected.
10 AM79C901A preliminary pin designations (pl 068) listed by pin number note: nc pins are reserved and should be left unconnected. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 led_link 18 dvdd 35 tdo 52 avss 2 led_col 19 rx_er 36 tck 53 tx+ 3 led_activity 20 dvss 37 tms 54 avdd 4 dvdd 21 gm_mode 38 tdi 55 tx- 5 led_power 22 tx_clk/txclk 39 xclk/xtal 56 avss 6 led_speed 23 tx_en/txen 40 xtal2 57 rx+ 7 dvss 24 txd0/txdat 41 xtal1 58 avdd 8 rxd3 25 txd1/sdi 42 avdd 59 rx- 9 rxd2 26 nc 43 nc 60 nc 10 rxd1 27 txd2 44 avdd 61 reset 11 rxd0/rxdat 28 txd3/cs 45 avss 62 ten 12 dvss 29 dvss 46 avss 63 mii/gpsi 13 rx_dv 30 col/cls 47 hrtxrxn 64 phy_ad 14 dvdd 31 dvss 48 avdd 65 isolate 15 rx_clk/rxclk 32 crs/rxcrs 49 hrtxrxp 66 mdio/sdo 16 avdd 33 dvdd 50 avdd 67 dvss 17 phy_sel 34 dvdd 51 iref 68 mdc/sclk
AM79C901A 11 preliminary pin designations (pqt 80) listed by pin number note: nc pins are reserved and should be left unconnected. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 21 nc 41 nc 61 nc 2 nc 22 nc 42 nc 62 nc 3 rxd1 23 txd2 43 avdd 63 reset 4 rxd0/rxdat 24 txd3/cs 44 avss 64 ten 5 dvss 25 dvss 45 avss 65 mii/gpsi 6 rx_dv 26 col/cls 46 hrtxrxn 66 phy_ad 7 dvdd 27 dvss 47 avdd 67 isolate 8 rx_clk/rxclk 28 crs/rxcrs 48 hrtxrxp 68 mdio/sdo 9 avdd 29 dvdd 49 avdd 69 dvss 10 phy_sel 30 dvdd 50 iref 70 mdc/sclk 11 dvdd 31 tdo 51 avss 71 led_link 12 rx_er 32 tck 52 tx+ 72 led_col 13 dvss 33 tms 53 avdd 73 led_activity 14 gm_mode 34 tdi 54 tx- 74 dvdd 15 tx_clk/txclk 35 xclk/xtal 55 avss 75 led_power 16 tx_en/txen 36 xtal2 56 rx+ 76 led_speed 17 txd0/txdat 37 xtal1 57 avdd 77 dvss 18 txd1/sdi 38 avdd 58 rx- 78 rxd3 19 nc 39 nc 59 nc 79 rxd2 20 nc 40 nc 60 nc 80 nc
12 AM79C901A preliminary pin designations (pl 068) listed by group pin name pin function type driver type number of pins configuration mii/gpsi selects mii or gpsi mode i ? 1 gm_mode selects mdc/mdio and gpsi data i ? 1 isolate isolates device if register isolate bit is set = 1 i ? 1 phy_sel defines default phy i ? 1 phy_ad defines bit 2 of the phy address i ? 1 board interface reset reset i ? 1 xclk/xtal oscillator/crystal select i ? 1 xtal1 crystal input (20 mhz xtal/60 mhz clk) i ? 1 xtal2 crystal output (20 mhz xtal) o xtal 1 iref tied to gnd via a 12.1 k ? 1% resistor i ? 1 led_col collision indication o led 1 led_activity activity indication o led 1 led_link link valid indication o led 1 led_speed high speed indication o led 1 led_power high power indication o led 1 1 mbps homepna phy network ports hrtxrxp/n receive/transmit data i/o ? 2 10base-t phy network ports tx serial transmit data o ? 2 rx serial receive data i ? 2 mii interface tx_clk mii transmit clock o omii 1 txd[3:0] mii transmit data i ? 4 tx_en mii transmit enable i ? 1 rx_clk mii receive clock o omii 1 rxd[3:0] mii receive data o omii 4 rx_er mii receive error o omii 1 rx_dv mii receive data valid o omii 1 mdc mii management data clock i ? 1 mdio mii management data input/output i/o tsmii 1 crs carrier sense o omii 1 col collision o omii 1
AM79C901A 13 preliminary pin name pin function type driver type number of pins gpsi interface txclk gpsi transmit clock o omii 1 txdat gpsi transmit data i ? 1 txen gpsi transmit enable i ? 1 rxclk gpsi receive clock o omii 1 rxdat gpsi receive data o omii 1 rxcrs carrier sense o omii 1 cls collision o omii 1 spi interface sclk spi clock i ? 1 sdi spi data in i ? 1 sdo spi data out o tsmii 1 cs chip select i ? 1 ieee 1149.1 (jtag) test access port interface tck test clock i ? 1 tms test mode select i ? 1 tdi test data in i ? 1 tdo test data out o ts 1 power supply dvdd digital power p ? 6 avdd analog power p ? 6 dvss digital ground g ? 7 avss analog ground g ? 3 test interface ten test enable i ? 1
14 AM79C901A preliminary pin designations (pqt 80) listed by group pin name pin function type driver type number of pins configuration mii/gpsi selects mii or gpsi mode i ? 1 gm_mode selects mdc/mdio and gpsi data i ? 1 isolate isolates device if register isolate bit is set = 1 i ? 1 phy_sel defines default phy i ? 1 phy_ad defines bit 2 of the phy address i ? 1 board interface reset reset i ? 1 xclk/xtal oscillator/crystal select i ? 1 xtal1 crystal input (20 mhz xtal/60 mhz clk) i ? 1 xtal2 crystal output (20 mhz xtal) o xtal 1 iref tied to gnd via a 12.1 k ? 1% resistor i ? 1 led_col collision indication o led 1 led_activity activity indication o led 1 led_link link valid indication o led 1 led_speed high speed indication o led 1 led_power high power indication o led 1 1 mbps homepna phy network ports hrtxrxp/n receive/transmit data i/o ? 2 10base-t phy network ports tx serial transmit data o ? 2 rx serial receive data i ? 2 mii interface tx_clk mii transmit clock o omii 1 txd[3:0] mii transmit data i ? 4 tx_en mii transmit enable i ? 1 rx_clk mii receive clock o omii 1 rxd[3:0] mii receive data o omii 4 rx_er mii receive error o omii 1 rx_dv mii receive data valid o omii 1 mdc mii management data clock i ? 1 mdio mii management data input/output i/o tsmii 1 crs carrier sense o omii 1 col collision o omii 1
AM79C901A 15 preliminary pin name pin function type driver type number of pins gpsi interface txclk gpsi transmit clock o omii 1 txdat gpsi transmit data i ? 1 txen gpsi transmit enable i ? 1 rxclk gpsi receive clock o omii 1 rxdat gpsi receive data o omii 1 rxcrs carrier sense o omii 1 cls collision o omii 1 spi interface sclk spi clock i ? 1 sdi spi data in i ? 1 sdo spi data out o tsmii 1 cs chip select i ? 1 ieee 1149.1 (jtag) test access port interface tck test clock i ? 1 tms test mode select i ? 1 tdi test data in i ? 1 tdo test data out o ts 1 power supply dvdd digital power p ? 6 avdd analog power p ? 6 dvss digital ground g ? 7 avss analog ground g ? 3 test interface ten test enable i ? 1
16 AM79C901A preliminary pin designations listed by driver type the following table describes the various types of out- put drivers used in the AM79C901A phy. all i ol and i oh values shown in the table apply to 3.3 v signaling. a sustained tri-state signal is an active-low signal that is driven high for one clock period before it is left floating. tx is a differential output driver. its characteristics and those of the xtal2 output are described in the dc characteristics section. note: for reference only. see dc specification for actual limits. driver name type i ol (ma) i oh (ma) load (pf) led led 12 0.4 50 ts tri-state 6 2 50 omii tri-state 4 4 50 tsmii tri-state 4 4 150
AM79C901A 17 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. temperature range c = commercial (0 c to +70 c) i = industrial ( ? 40 c to +85 c) speed option package type valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations device number/description not applicable j = plastic leaded chip carrier (pl 068) v = thin plastic quad flat pack (pqt 80) AM79C901A homephy single-chip 1/10 mbps home networking phy valid combinations AM79C901A jc, jc\t vc, vi alternate packaging optio n \t = tape and reel c\i j\v \t AM79C901A
18 AM79C901A preliminary pin descriptions configuration pins mii/gpsi mii/gpsi input mii/gpsi selects between the mii and the gpsi inter- face. this pin must be connected to either v dd or v ss . changing the state of this pin is prohibited. gm_mode gm_mode input this input pin selects between the mdc/mdio com- mand and control interface and the spi interface nor- mally available in the gpsi mode. this pin must be connected to either v dd or v ss . changing the state of this pin is prohibited. note: gm_mode = 1 overrides the value on the mii/gpsi configuration pin. phy_ad phy address input sets bit 2 of the phy address field. the phys have de- fault mii address of 0x00 (0000b) for the 1 mbps homepna phy and 0x01 (0001b) for the 10base-t phy. if this bit is set, the address for the homepna phy is 0x02 (00010b) and 0x03 (00011b) for the 10base-t phy. isolate isolate input in an environment that utilizes the mii or the spi com- mand and control interface (managed mode), this pin must be held high. in an environment that does not use the mii or the spi command and control interface (external control mode), this pin enables the data inter- face when set to a low, and forces the interface into a high impedance state when held high. this pin func- tions in conjunction with the phy_sel pin and hpr0, bit 10, and tbr0, bit 10. phy_sel phy select input in an environment that utilizes the mii or the spi com- mand and control interface (managed mode), this pin must be held low. in an environment that does not use the mii or the spi command and control interface (ex- ternal control mode), this pin selects which phy data and status signals will be driven onto the interface. when set to a low, the homepna phy data and sta- tus signals will be driven onto the interface. when set to a high, the 10base-t phy data and status signals will be driven onto the interface. this pin functions in conjunction with the isolate pin. low = 1 mbps homepna phy high = 10base-t phy board interface led_col led_col output this output is designed to directly drive an led. col low indicates that a collision has been detected on the currently active phy. an internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. led_activity led_activity output this output is designed to directly drive an led. activity low indicates that there is receive or trans- mit activity on the network of the currently active phy. an internal pulse stretching circuit will ensure that the minimum output pulse is approximately 100 ms. led_link led_link output this output is designed to directly drive an led. link low indicates that a valid link has been detected on the currently active phy. gm_mode mii/gpsi data interface command and control interface 0 1 mii mdc/mdio 0 0 gpsi spi 1 x gpsi mdc/mdio hpr0 bit 10 t b r 0 bit 10 phy_sel isolate interface source managed mode 11 0 1 hi z 01 0 1 1 mbps homepna 1 0 0 1 10base-t 00 0 1 non valid external control mode 1 1 1 0 10base-t 11 0 0 1 mbps homepna 11 don ? t care 1hi z
AM79C901A 19 preliminary led_speed led_speed output this output is designed to directly drive an led. speed low indicates that the homepna phy is currently in the high-speed mode. when operating in the 10base-t mode this output will be held high. led_power led_power output this output is designed to directly drive an led. power low indicates that the homepna phy is cur- rently in high-power mode. when operating in the 10base-t mode this output will be held high. reset reset input the reset is an active-low, asynchronous reset signal. this signal must be held low for a minimum of 5 s and requires 60 s for recovery after the rising edge of reset . gpsi interface rxdat receive data output rxdat is the serial data received from the selected port. data on rxdat is driven on the falling edge of rxclk. rxclk receive data clock output rxclk provides the timing reference for transfer of the receive data. rxclk is driven by the device and operates at a maximum frequency of 10 mhz. rxcrs receive carrier sense output the rxcrs pin is active during receive or transmit ac- tivity for the homepna phy or during receive (based on tbr17, bit 2) for the 10base-t phy. cls collision output this signal is asserted whenever a collision is detected on the transmit and receive path of the selected port. this signal will also be asserted for ~1 s within 40 s after the negation of the txen signal in support of the sqe test. the sqe functionality may be controlled via tbr17, bit 11, and hpr16, bit 12. txdat transmit data input txdat is the serial data driven from the mac. data on txdat is latched on the falling edge of txclk. txclk transmit data clock output txclk provides the timing reference for transfer of the transmitted data. txclk is driven by the device and operates at a maximum frequency of 10 mhz. txen transmit enable input txen indicates when the mac device is presenting valid transmit data on the txdat pin. txen must be asserted with the first bit of preamble and remain as- serted throughout the duration of the packet until it is deasserted prior to the first txclk following the final bit of the frame. txen transitions are synchronous to txclk. spi interface (slave mode only) sclk spi clock input sclk is driven from the controlling device as a timing reference for transfer of information on the sdi and sdo signals. the maximum clock frequency is 2.5 mhz. cs spi chip select input this pin is used to enable the AM79C901A for slave mode transfers. when this pin is inactive (high), the device ignores sclk and sdi inputs and holds sdo in high-impedance. sdi spi serial data in input this data line provides input data from the master de- vice to the AM79C901A. the data presented on this pin is latched on the rising edge of sclk. sdo spi serial data out output this data line provides output data from the AM79C901A to the master device. to provide for a ro- bust interface, this data is driven on the rising edge of sclk. mii interface rx_clk receive clock output rx_clk is a clock input that provides the timing ref- erence for the transfer of the rx_dv, rxd[3:0], and rx_er signals from the AM79C901A device. rx_clk will provide a nibble rate clock. it operates at a maximum frequency of 2.5 mhz.
20 AM79C901A preliminary rxd[3:0] receive data output rxd[3:0] is the nibble-wide receive data bus. data on rxd[3:0] is driven on the falling edge of rx_clk. rxd[3:0] should be ignored while rx_dv is deasserted. rx_dv receive data valid output rx_dv is an output used to indicate that valid received data is being presented on the rxd[3:0] pins and rx_clk is synchronous to the receive data. rx_dv will be asserted prior to the rx_clk rising edge, when the first nibble of the start of frame delimiter (sfd) is driven on rxd[3:0], and will remain asserted until after the rising edge of rx_clk, when the last nibble of the crc is driven on rxd[3:0]. rx_dv will be deasserted prior to the rx_clk rising edge which follows this final nibble. rx_dv transitions are driven on the falling edge of rx_clk. crs carrier sense output the crs pin is active during receive or transmit activity for the homepna phy or during receive (based on tbr17, bit 2) for the 10base-t phy. col collision output this signal is asserted whenever a collision is detected on the transmit and receive path of the selected port. this signal will also be asserted for ~1 s within 40 s after the negation of the txen signal in support of the sqe test. the sqe functionality may be controlled via tbr17, bit 11, and hpr16, bit 12. rx_er receive error output rx_er is an output for the 10base-t phy that indi- cates that the transceiver device has detected a coding error in the receive data frame currently being trans- ferred on the rxd[3:0] pins. rx_er is ignored while rx_dv is deasserted. special code groups generated on rxd while rx_dv is deasserted are ignored (e.g., bad ssd in tx and idle in t4). rx_er transitions are synchronous to rx_clk. tx_clk transmit clock output tx_clk is a clock output that provides the timing ref- erence for the transfer of the txd[3:0] and tx_er sig- nals from the AM79C901A device. tx_clk provides a nibble rate clock. txd[3:0] transmit data input txd[3:0] is the nibble-wide data bus. valid data is gen- erated on txd[3:0] on every rising edge of tx_clk while tx_en is asserted. while tx_en is deasserted, txd[3:0] values are ignored. txd[3:0] transitions are latched on the falling edge of tx_clk. tx_en transmit enable input tx_en indicates that the mac device is presenting valid transmit data on the txd[3:0] bus. tx_en must be asserted with the first nibble of preamble and re- mains asserted throughout the duration of the packet until it is deasserted prior to the first tx_clk following the final nibble of the frame. tx_en transitions are latched on the falling edge of tx_clk. mdc management data clock input mdc is the non-continuous clock input that provides a timing reference for bits on the mdio pin. during mii management port operations, mdc runs at a nominal frequency of 2.5 mhz. mdio management data input/output input/output mdio is a bidirectional mii management port data pin. mdio is an input during the header portion of the man- agement frame transfers and during the data portion of write operations. mdio is an output during the data portion of read operations. the mdio pin should be externally pulled up to v dd with a 1.5 k ? 5% resistor. ieee 1149.1 (jtag) test access port interface tck test clock input tck is the clock input for the boundary scan test mode operation. it can operate at a frequency of up to 10 mhz. tck has an internal pull-up resistor. tdi test data in input tdi is the test data input path to the AM79C901A phy. the pin has an internal pull-up resistor. tdo test data out output tdo is the test data output path from the AM79C901A phy. the pin is tri-stated when the jtag port is inactive.
AM79C901A 21 preliminary tms test mode select input a serial input bit stream on the tms pin is used to de- fine the specific boundary scan test to be executed. the pin has an internal pull-up resistor. ethernet network interfaces tx serial transmit data output these pins carry the transmit output data and are con- nected to the transmit side of the magnetics module. rx serial receive data input these pins accept the receive input data from the magnetics module. iref internal current reference input this pin serves as a current reference for the integrated 1/10 phy. it must be connected to gnd through a 12.1 k ? resistor (1%). homepna phy network interface hrtxrxp/hrtxrxn serial receive data input/output these pins accept the receive input data from the mag- netics module and carry the transmit output data. a 102- ? resistor should be placed between these pins. clock interface xclk/xtal external clock/crystal select input when high, an external 60-mhz clock source is se- lected bypassing the crystal circuit and clock trippler. when low, a 20-mhz crystal is used instead. table 1 illustrates how this pin works. table 1. clock source selection xtal1 crystal oscillator in input the internal clock generator utilizes either a 20-mhz crystal that is attached to pins xtal1 and xtal2 or a 60-mhz clock source connected to xtal1. this pin is not 5 v tolerant, and the 60 mhz clock source should be from a 3.3 v source. xtal2 crystal oscillator out output the internal clock generator utilizes a 20-mhz crystal that is attached to pins xtal1 and xtal2. in xclk mode, this pin should be left unconnected. power supply dvdd digital power (5 pins) +3.3 v power these pins are the power supply pins that are used to provide power to the digital portions of the design. all dvdd pins must be connected to a +3.3 v supply. avdd analog power (7 pins) +3.3 v power these pins are the power supply pins that are used to provide power to the analog portions of the design. all avdd pins must be connected to a +3.3 v supply. dvss digital ground (6 pins) ground these pins are the ground connections for the digital portions of the design. avss analog ground (4 pins) ground these pins are the ground connections for the analog portion of the design. scan test interface ten test enable input the test enable pin is for factory use only. it must be connected to v ss for normal operation. input pin output pin xclk/xtal clock source xtal1 xtal2 0 20-mhz crystal xtal1 nc 1 60-mhz oscillator/ external clk source
22 AM79C901A preliminary basic functions network interfaces the AM79C901A phy contains an integrated 1 mbps home networking phy and a 10base-t phy. this de- vice is compliant with the homepna specification 1.0 and ieee 802.3 specification. the integrated homepna transceiver is a physical layer device that enables data networking at speeds up to 1 mbps over existing residential phone wiring regard- less of topology and without disrupting telephone (pots) service. the integrated ethernet transceiver is a physical layer device supporting the ieee 802.3 standard for 10base-t. it provides all of the phy layer functions re- quired to support 10 mbps data transfer speeds. the 10base-t phy supports both half-duplex and full-duplex operation. phy data interfaces the AM79C901A phy has both gpsi and mii-com- patible data interfaces. in addition, a special mode, gm_mode, allows access to the mdc/mdio com- mand and control interface while in the gpsi mode. for more information, see the pin descriptions and the detailed functions sections. reset there are two different types of reset operations that may be performed on the AM79C901A device, h_reset or s_reset. the following is a description of each type of reset operation. h_reset hardware reset (h_reset) is a reset operation that has been initiated by the proper assertion of the reset pin of the AM79C901A device. when the minimum pulse width timing as specified in the reset pin description has been satisfied, an inter- nal reset operation will be performed. h_reset will program all of the registers to their default value. s_reset in a software reset (s_reset), programming bit 15 of hpr0 to 1 will reset all the registers in the 1 mbps homepna phy (hprs), and programming bit 15 of tbr0 to 1 will reset tbr4, tbr7, tbr17, and tbr24 in the 10base-t phy. these bits are self-clearing. detailed functions gpsi interface the seven signals that comprise the gpsi are txclk, txen, txdat, rxclk, rxcrs, rxdat, and cls. of these, only txen and txdat are inputs to the phy; the other five are outputs from the phy. these signals behave differently depending on which operation is cur- rently happening in the phy. the operations of the phy are as follows: idle (no activity in either direction), rxpkt (receiving data), and txpkt (transmitting data). the subsequent subsections analyze each gpsi-related state of the phy in detail. figure 1. idle state txclk txen txdat rxclk rxcrs rxdat cls note : rxclk and txclk are synchronized to the same phase. all other signals are inactive. the two clock signals toggle for an overall period of 583.3ns (about 1.7 mhz). 22304b-3
AM79C901A 23 preliminary figure 2. rxpkt - rxcrs asserted figure 3. rxpkt - rxcrs cleared txclk txen txdat rxclk rxcrs rxdat cls 22304b-4 note: rxclk becomes disabled as soon as rxcrs is asserted. txclk txen txdat rxclk rxcrs rxdat cls note: rxclk and txclk are unrelated to each other during this time. when a symbol has been received and decoded, rxclk toggles in order to shift out the three to six bits encoded in the symbol. the middle portion of this diagram shows the end of the preamble, followed by an sfd and the beginning of the data. rxcrs will fall after the last received symbol. once rxcrs falls, rxclk and txclk are toggled continuously for 96 cycles, after which the phy returns to the idle state. 22304b-5
24 AM79C901A preliminary figure 4. txpkt - txen asserted figure 5. txpkt - rxclk active txclk txen txdat rxclk rxcrs rxdat cls note : once txen is asserted, the phy stops rxclk, asserts rxcrs, and toggles txclk. 22304b-6 txclk txen txdat rxclk rxcrs rxdat cls 22304b-7 note : txclk continues to toggle until the sfd is observed, as shown in the first section of the above diagram. at this point, txclk is disabled (low) until the aid header has been transmitted on the wire (or until a cls has been detected). at this time rxclk starts toggling, thereby, shifting 32 bits of preamble and sfd back to the mac. sometime later, the txclk restarts as symbols get sent onto the wire in an analogous manner as rxclk during packet reception.
AM79C901A 25 preliminary figure 6. txpkt - txen cleared figure 7. txpkt - cls asserted txclk txen txdat rxclk rxcrs rxdat cls 22304b-8 note : once txen is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the mac, and rxcrs falls. once rxcrs falls, txclk and rxclk toggle for 96 clocks, after which the system returns to the idle state. txclk txen txdat rxclk rxcrs rxdat cls note: cls will be asserted some time after the preamble and sfd have been clocked in. txclk and rxclk are then clocked until rxcrs drops. txen drops about 32 clocks after cls was asserted. rxcrs and cls are dropped together after more than 500 clocks (about 120 s). txclk and rxclk keep toggling for approx- imately another 100 clock cycles, when the system returns to the idle state. 22304b-9
26 AM79C901A preliminary figure 8. rxpkt - cls asserted table 2. gpsi timing note: during the aid interval, txclk and rxclk stop for up to 140 s. serial peripheral interface (spi-slave) mode when mii/gpsi is set to 0, the device is in ? spi ? mode. the device acts as an spi slave peripheral in this mode of operation. commands are issued to the device by asserting the cs signal (active low), shifting in an 4-bit opcode, followed by an 10-bit register address and 2 bits of end delimiter. if the operation is a write, the data bits are written into the desired register. if the op- eration is a read, then these data bits are ignored. the sdo pin will shift out 16 data bits representing the con- tents of the register referenced by the address field for read operations. all commands must be initiated with a high-to-low transition on the cs pin. only one com- mand can be sent in one cs cycle. for assistance in debugging access to the spi inter- face, an error code is driven onto the sdo. if there is less than 32 bits of sclk during the time that cs is as- serted, the error code field of sdo on the next com- mand will indicate aaaa. when there is an incorrect opcode in the command on sdi aaaa will be immedi- ately driven out on sdo until cs deasserts. if there are more than 32 clock cycles while cs is low, the first 32 are assumed to contain the data, and the additional clock bits and associated data are ignored. in this case, the sdo might generate aaaa under the additional clock bits. see figure 9. figure 9. operation of the spi interface txclk txen txdat rxclk rxcrs rxdat cls 22304b-10 note: cls may be asserted up to 120 s after rxcrs has been asserted. once cls has been asserted, txclk and rxclk run until 96 cycles after cls and rxcrs are cleared. it can take a maximum of approxi- mately 60 s for rxcrs to clear. condition clk period clk frequency idle (excluding ipg time) 583.3 ns 1.7 mhz preamble (first 64 bits of tx mac frame) 233.3 ns 4.3 mhz data (throughout the data phase) 1 0 0 n s - 10 s 1.0 mhz avg. ipg (96 bit times following crs ) 233.3 ns 4.3 mhz sclk cs sdi sdo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 op codes address data in data out error code 22304b-11
AM79C901A 27 preliminary table 3. spi op codes figure 10. spi read operation figure 11. aborted operation of the spi interface figure 12. first operation following an abort sdi op codes address data in st op phyadd regadd ed read 01 10 aaaaa rrrrr 10 don ? t care write 01 01 aaaaa rrrrr 10 d15 ??? d0 sdo error code data out read 0000 = no error/aaaa = error detected d15...d0 write 0000 = no error/aaaa = error detected don ? t care 31 32 15 16 17 18 1234 sclk sdo sdi cs start frame read command end delimiter first data bit last data bit 22304b-12 sclk cs sdi sdo 1 2 3 4 5 6 7 8 9 10 11 12 13 op codes address error code = 0 22304b-13 sclk cs sdi sdo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 op codes address data in data out error code = aaaa 22304b-14
28 AM79C901A preliminary figure 13. normal operation mii-compatible interface for homepna phy the control and data signals that are utilized in the mii- compatible interface of the 1 mbps homepna phy function in an manner that is identical to that as defined in the 802.3u specification. the signals rx_clk and tx_clk function in a slightly different manner in that they operate at a reduced data rate and that these clock signals do not run at a constant rate due to the rll25 ? encoding scheme. see table 4. table 4. mii-compatible timing note: during the aid interval, tx_clk and rx_clk stop for up to 140 s. figure 14 and figure 15 represent the signal relation- ships when the mii-compatible data interface is utilized. the signals tx_clk and rx_clk will toggle at a rate of approximately 428 khz during idle time. when the tx_en signal is asserted to indicate the beginning of a transmission, the clock rate will enter the preamble phase. once the sfd has been detected and the homepna phy has begun the transmission of the homepna header, the clock enters the data phase. when the tx_en signal is deasserted to indicate the ending of a transmission, tx_clk is halted until the rxdata path detects the end of the packet. at this time, the clock rate is increased to the ipg data rate for 96 bit times and then returns to the idle state. mii-compliant interface for 10base-t phy the mii interface is fully ieee 802.3u-compliant when the 10base-t phy is selected. the management in- terface specified in clause 22 of the ieee 802.3u stan- dard provides for a simple two wire, serial interface to connect a management entity and a managed phy for the purpose of controlling the phy and gathering sta- tus information. the two lines are management data input/output (mdio) and management data clock (mdc). a station management entity, which is attached to multiple phy entities, must have prior knowledge of the appropriate phy address for each phy entity. the management interface physically transports man- agement information across the mii. the information is encapsulated in a frame format as specified in clause 22 of the ieee 802.3u standard and is shown in table 5. table 5. mii control frame format 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 31 32 op codes address data in data out error code = 0 sclk cs sdi sdo 22304b-15 condition clk period clk frequency idle (excluding ipg time) 2333.34 ns 428.6 khz preamble (first 64 bits of tx mac frame) 933.33 ns 1.07 mhz data (throughout the data phase) 400 ns - 40 s250 khz avg. ipg (96 bit times following crs ) 933.33 ns 1.07 mhz pre st op phyadd regadd ta data idle read 1...1 01 10 aaaaa rrrrr z0 d15 ??? d0 z write 1...1 01 01 aaaaa rrrrr 10 d15 ??? d0 z
AM79C901A 29 preliminary the operation field (op) follows the start field (st). the op indicates whether the operation is a read or a write operation. the phy address (phyadd) and the register address (regadd) that were programmed follow this. a bus turnaround field (ta) follows the re- gadd field. during the read operation, the bus ta field is used to determine if the phy is responding properly to the read request. the final field is the idle field, and it is required to allow the drivers to turn off. the phyadd field, which is five bits wide, allows 32 unique phy addresses. the managed phy layer de- vice that is connected to a station management entity via the mii interface has to respond to transactions ad- dressed to the phy ? s address. a station management entity attached to multiple phys is required to have prior knowledge of the appropriate phy address. for more information, see the ieee 802.3 specification and the mii pin descriptions. figure 14. mii start of transmission tx_clk tx_en txd crs rx_clk rx_dv rxd 55 idle preamble data d 55 55 55 d 2 col 22304b-16
30 AM79C901A preliminary figure 15. mii end of transmission tx_clk tx_en txd crs 96 bit times rx_clk rx_dv rxd ipg idle data data 55 55 data col if seq is enabled 22304b-17
AM79C901A 31 preliminary 1 mbps homepna phy the integrated homepna transceiver is a physical layer device supporting homepna specification 1.0 for home phoneline networking. it provides all of the phy layer functions required to support 1 mbps data transfer speeds over existing residential phone wiring. all data bits are encoded into the relative time position of a pulse with respect to the previous one. the wave- form on the wire consists of a 7.5 mhz carrier sinusoid enclosed within an exponential (bell shaped) enve- lope. the waveform is produced by generating four 7.5 mhz square wave cycles and passing them through an external bandpass filter. the homepna phy frame consists of a homepna header that replaces the normal ethernet 64-bit pream- ble and delimiter. the frame header is prepended to a standard ethernet packet starting with the destination address and ending with the crc. only the phy layer and its parameters are modified from that of the standard ethernet implementation. the homepna phy layer is designed to operate with a standard ethernet mac layer controller implementing all the csma/cd protocol features. the frame begins with a characteristic sync interval that delineates the beginning of a homepna frame fol- lowed by an access id (aid) which encodes 8 bits of aid and 4 bits of control word. the aid is used to de- tect collisions and is dynamically assigned, while the control word carries speed and power information. the aid is followed by a silence interval, then 32 bits of data reserved for phy layer communication. these bits are accessible via internal registers and are for future use. data encoding consists of two symbol types: an aid symbol and a data symbol. the aid symbol is always transmitted at the same speed and encodes 2 bits that determine the pulse position (one of four) relative to the previous pulse. these bits are transmitted lsb first. the access symbol interval is fixed. the data symbol interval is variable. the arriving bit stream is blocked into from 3-bit to 6-bit blocks accord- ing to a proprietary (rll25) algorithm. the bits in each block are then used to encode a data symbol. each symbol consists of a data inter symbol blanking inter- val (disbi) and then a pulse at one of 25 possible po- sitions. the bits in the data block determine the pulse position. immediately after the pulse a new symbol in- terval begins. during the disbi the receiver ignores all incoming pulses to allow network reflections to die out. any station may be programmed to assume the role of a phy master and remotely command, via the control word, the rest of the units on the network to change their transmit speed or power level. many of the framing parameters are programmable in the homepna phy and will allow modifications to transmission speed center frequency as well as noise and reflection rejection algorithms. two default speeds are provided, low at 0.7 mbps and high at 1 mbps. homepna phy medium interface framing the homepna frame on the phone wire network con- sists of a header generated in the phy prepended to an ieee 802.3 ethernet data packet received from the mac layer. see figure 16. when transmitting on the phone wire pair, the homepna phy first receives an ethernet mac frame from the mac. the 8 octets of preamble and delimiter are stripped off and replaced with the homepna phy header described below, then transmitted on the home network with the lsb of each symbol being transmitted first. during a receive operation, the reverse process is exe- cuted. when a homepna phy frame is received by the phy, the header is stripped off and replaced with the 4 octets of preamble and delimiter of the ieee 802.3 ethernet mac frame specification and then passed on to the mac layer.
32 AM79C901A preliminary figure 16. homepna phy framing homepna phy symbol waveform all homepna phy symbols are composed at the transmit- ter of a silence interval and a pulse formed of an integer number of cycles (tx_pulse_cycles_p/n in hpr29) of a square wave of frequency (center_frequency tx_pulse_width in hpr29) that has been filtered with an external bandpass filter. data is encoded in the time in- terval from the preceding pulse. table 6. homepna phy pulse parameters time interval unit homepna phy time intervals are expressed in time interval clock (tic) units. one tic is defined as 7/60e6 seconds or approximately 116.7 ns. access id intervals a homepna frame begins with an access id (aid) in- terval which is composed of eight equally spaced sub- intervals termed aid symbols 0 through 7 as shown in figure 17. an aid symbol is 129 tics long. transmit timing is shown in figure 17; receive timing in figure 18. timing starts at the beginning of each aid symbol at tic = 0 and ends at tic = 129. these symbols are described in the following sections. symbol 0 (sync interval) sync transmit timing : the sync interval (aid sym- bol 0) delineates the beginning of a homepna phy frame and is composed of a sync_start pulse, fol- lowed by a sync_end pulse, after a fixed silence in- terval as shown in figure 17. timing for this (aid symbol 0) starts (tic = 0) at the beginning of the sync_start pulse. the sync_end pulse starts at tic = 126. at tic = 129, this aid symbol 0 ends and the next aid symbol begins, with the symbol timing reference reset to tic = 0. no information bits are coded in the sync (aid symbol 0 interval). sync receive timing : as soon as the sync_start pulse is detected the receiver disables (blanks) further detection until time tic = 61, after which detection is re-enabled for the next received pulse. the receiver al- lows for jitter by establishing a window around each legal pulse position. this asymmetrical window is two tics wide on one side of the position and one tic wide on the other. a sync_end pulse that arrives outside the window of the legal tic = 126 is considered a noise event which is used in setting the adaptive squelch level, aborts the packet, and sets the receiver in search of a new sync_start pulse and sync interval. if it is a trans- mitting station, the collision event is asserted as described in the collisions section. sync interval access id silence pcom 4 source 6 destination length 2 ethernet mac and data max 1500 crc 4 32 bits pcom ethernet packet fixed 14.93 s aid blanking interval aid blanking interval aid blanking interval aid blanking interval aid blanking interval aid blanking interval 01 11 10 00 01 00 60 tics 129 tics 129 tics 129 tics 129 tics 129 tics 129 tics 129 tics data symbols 20 tics 66 tics silence interval sync symbol 0 access id symbol 1 access id symbol 2 access id symbol 3 access id symbol 4 access id symbol 5 access id symbol 6 access id symbol 7 30.75 s @ 1 mbps access id interval example access id of 01110100 and control word 0100 fixed 120.39 s homepna phy header 151.14 s @ 1 mbps 1 tic = 116.6667 ns homepna header ethernet packet pulse 129 tics = receiver blanking interval potential pulse position 6 22304b-18 note : using default configurations. parameter value tolerance unit center_frequency 7.5 500 ppm mhz cycles_per_pulse 4 ? cycles
AM79C901A 33 preliminary figure 17. aid symbol transmit timing figure 18. aid symbol receive timing the sync interval is followed by six aid symbols (symbols 1 through 6). transmit timing is shown in fig- ure 17; receive timing in figure 18. data is encoded in the relative position of each pulse with respect to the previous one. a pulse may occur at one, and only one, of the four possible positions within an aid symbol yielding two bits of data coded per aid symbol. the decoded bits from the aid symbols 1 to 4 produce eight bits of access id which is used to identify individ- ual homepna stations and to detect collisions. the msb is encoded in aid symbol 1 and is the leftmost bit in table 7. table 7. access id symbol pulse positions and encoding aid symbol 0 aid symbol 1 aid symbol 2 pulse 2 shown in position 1 pulse 0 pulse 1 tic=129 and tic=0 tic=129 and tic=0 sync_start tic=0 sync_end tic=126 aid_position_0 tic=66 aid_position_1 tic=86 aid_position_2 tic=106 aid_position_3 tic=126 transmitter 22304b-19 aid symbol 0 aid symbol 1 aid symbol 2 pulse 2 shown in position 1 pulse 0 pulse 1 tic=129 and tic=0 tic=129 and tic=0 sync_start tic=0 sync_end tic=126 aid_position_0 tic=66 aid_position_1 tic=86 aid_position_2 tic=106 aid_position_3 tic=126 receiver d slice threshold end_rcv_blank aid_guard_interval detected envelope 22304b-20 pulse position tics from beginning of aid symbol bit encoding 166 00 286 01 3106 10 4126 11
34 AM79C901A preliminary the next two aid symbols (5 and 6) encode four bits of control word information. the msb is encoded in aid symbol 5. control word messages are described further in the mode interface section. aid transmit timing : the transmitter encodes the ac- cess id in a pulse position in each 129 tic interval. each aid symbol interval must have only one pulse. pulse transmission must start in only one of the four possible positions (measured from the beginning of the access id symbol) defined in table 7. aid receive timing : the receiver allows for jitter by establishing a window around each legal pulse posi- tion. this asymmetrical window is two tics wide on one side of the position and one tic wide on the other. a pulse that arrives outside of the legal aid positions is considered a collision event. collisions a collision is detected only during access id and silent intervals (aid symbols 0 through 7). in general during a collision, a transmitting station will read back an aid value that does not match its own, recognize the event as a collision, and alert other stations with a jam sig- nal. non-transmitting stations may also detect some collisions by interpreting received non-conforming aid pulses as collisions. with two transmitters colliding, each transmitter nor- mally blanks its receive input immediately after trans- mitting (and simultaneously receiving) a pulse. therefore, only when a transmitting station receives pulses in a position earlier than the position it transmit- ted will it recognize it as a pulse transmitted by another station and signal a collision. for this reason, guaranteed collision detection is pos- sible only as long as the spacing between successive possible pulse positions in an aid symbol (20 tics or 2.3 s) is greater than the roundtrip delay between the colliding nodes. at approximately 1.5 ns propagation delay per foot, the maximum distance between two homepna units must not be greater than 500 feet for collision detection purposes (1.5 s roundtrip delay plus margin). the following criteria must be met to guarantee reliable collision detection: at least one homepna station of a colliding group must always detect a collision when the delay between the beginning of its transmitted packet and the beginning of the received colliding packet is between -1.5 s and +1.5 s. in general, any received pulse at a homepna station that does not conform to the pulse position require- ments of aid symbols 0 through 7 shall indicate a col- lision on the wire. when a transmitting station senses a collision, it emits a jam signal to alert all other sta- tions to the collision. the following conditions signify a collision event: 1. a homepna station receives an aid that does not match the one being sent. 2. a homepna station receives a pulse outside the aid_guard interval in aid intervals 0 to 7. 3. a homepna station receives a pulse inside the silent_interval (aid symbol 7). as in all cases, pulses received during a blanking interval are ignored. passive stations (stations not actively transmitting dur- ing the collision) cannot reliably detect collisions. therefore, once a collision is detected by a transmitting station, the station must inform the rest of the stations of the collision with a jam pattern described below. only a transmitting station emits a jam signal. once a collision is detected, the collision signal to the mac interface is asserted and is not reset until the mac deactivates the txen signal. jam signal a jam pattern consists of 1 pulse every 32 tics and continues until at least the end of the aid intervals. after the aid interval, the jam pattern will continue until txen from the mac is deactivated. access id values the access id values for stations are randomly picked by each individual station from the set of aid numbers described in the management section. during opera- tion, each homepna station monitors homepna frames received on the wire. if it detects another home- pna station using the same aid, it will select a new random aid. silence interval (aid symbol 7) the access id symbols are followed by a fixed silence interval of 129 tics. the receive blanking interval is the same as that of the aid symbols (1 through 6). any pulses detected in the silence interval are consid- ered a collision event for transmitting stations and are handled as described in the collisions section. data symbols data symbols encode data for a much higher transmis- sion rate, and they do not allow collision detection.
AM79C901A 35 preliminary data transmit timing a data symbol interval begins with the start of transmis- sion of a pulse as shown in figure 19. transmit symbol timing (in tics) is measured from this point (tic = 0). depending on the data code, the next pulse may begin at any pulse_position_n where n = 0 to 24. each position is separated from the previous one by one tic. pulse_position_0 occurs at a value defined in table 8 which determines the transmission speed. when a pulse begins transmission, the previous sym- bol interval ends and a new one begins immediately. table 8. blanking interval speed settings figure 19. transmit data symbol timing data receive timing the incoming waveform is formed from the transmitted pulse along with any distortions and reflections that occur in the wiring network. the receiver detects the point at which the envelope of the received waveform crosses a set threshold. see figure 20. immediately after the threshold crossing, the receiver disables any further detection for a period isbi-3 tics (hpr28, isbi_slow or isbi_fast) starting with the detection of the pulse peak. the receiver is then re-enabled for pulse detection. upon reception of the next pulse, the receiver mea- sures the elapsed time from the previous pulse. this value is then placed in the nearest pulse posi- tion bin (one of 25) where pulse position 0 is at pulse_position_0 and each subsequent posi- tion is spaced one tic from the previous one as de- fined in the data transmit timing section. data symbol intervals are therefore variable and depend on the encoded data. figure 20. receive symbol timing speed setting nominal data rate pulse_position_0 value (in tics) low_speed 0.7 mbps 44 high_speed 1.0 mbps 28 symbol 1 symbol 2 pulse 0 data blanking interval (disbi) pulse 1 pulse 2 1 tic s tart_tx_pulse t ic=0 end_tx_pulse time pulse_position_0 time position 1 position n1 position 0 position 1 position n2 n=0-24 transmitter 22304b-21 symbol 1 symbol 2 pulse 0 detected envelope pulse 1 pulse 2 e gin of receive anking interval end_data_blank position 1 position n1 position 0 position 1 position n2 position 0 d ata slice t hreshold receiver 22304b-22
36 AM79C901A preliminary data symbol rll25 encoding the rll25 code is the version of tm32 that was devel- oped for the homepna phy. it produces the highest bit rate for a given value of isbi and tic size. in a manner similar to run length limited disk coding, rll25 en- codes data bits in groups of varying sizes, specifically: 3, 4, 5, and 6 bits. pulse positions are assigned to the encoded bit groups in a manner, which causes more data bits to be encoded in positions that are farther apart. this keeps both the average and minimum bit rates higher. data symbol rll25 codes data by traversing a tree as illustrated in figure 21. assuming that successive data bits are encoded and labeled a, b, c, d, ? , etc., the en- coding process begins at the root node and proceeds as follows: 1. if the first bit (bit a) is a one, the next three bits (b, c, and d) select which one of the eight positions 1-8 is transmitted. the encoding process then continues at the root node. 2. if bit a is a zero and bit b is a one, the next three bits (c, d, and e) select which one of the eight positions 9-16 is transmitted. the encoding process then continues at the root node. 3. if bit a is a zero, bit b is a zero, and bit c is a one, the next three bits (d, e, and f) select which one of the eight positions 17-24 is transmitted. the encoding process then continues at the root node. 4. finally, if bits a, b, and c are all zeros, position 0 is transmitted. the encoding process then continues at the root node. as a result, symbol 0 encodes the 3-bit data pattern 000, positions 1-8 encode the 4-bit data pattern 1bcd, positions 9-16 encode the 5-bit data pattern 01cde, and positions 17-24 encode the 6-bit data pattern 001def. if the data encoded is random, 50% of the po- sitions used will be for 4-bit patterns, 25% will be for 5- bit patterns, 12.5% will be for 6-bit patterns, and 12.5% will be for 3-bit patterns. mode interface the homepna phy may be managed from either of two interfaces (the managed parameters vary depending on the interface): 1. remote control-word management commands embedded in the homepna aid header on the wire network. 2. management messages from a local management entity. figure 21. rll 25 coding tree c d these select position 1 - 8 a b e f awaiting coding and transmission encoded and sent start: examine the next bits to be encoded c d 1 b these select position 9 - 16 c d 0 1 e these select position 17- 24 1 d 0 0 e f 0 0 0 a = ? b = ? c = ? 1 1 1 1 0 0 0 send symbol 1-8 send symbol 9-16 send symbol 17-24 send symbol 0 data stream from mac controller 22304b-23
AM79C901A 37 preliminary header aid remote control word commands stations may be configured either as master stations or as slave stations. only one master may exist on a given homepna segment or network over which the homepna phy header is preserved. the master station may send commands embedded in the homepna header control word to remotely set var- ious parameters of the remote slave stations. stations are identified via the aid as follows: 1. the master station is identified on the homepna wire network with an aid of ffh. 2. a slave is identified with an aid of 00h to efh. 3. aid values of f0h to feh are reserved for future use. once a command has been transmitted, the master station will revert to a slave aid, so that subsequent control words are not interpreted by the slave stations as new commands. master mode is entered by writing to the phy control register (hpr16, bits 8 to 11) and is exited upon the completion of the command sequence. a valid master remote command consists of three homepna frames with an aid of ffh. since the homepna phy header is prepended to packets re- ceived from the mac, as well as any1home packets, packets from the master station may be separated by intervals during which other (slave) stations may transmit their frames. a remote master control word command will be recog- nized and executed by a homepna phy when it re- ceives three consecutive valid homepna frames with an aid of ffh. valid commands are as follows: 1. set_power: commands slave stations to set their transmit level to a prescribed level until another master command is received. 2. set_speed: commands slave stations to set their transmit speed to a prescribed value until another master command is received. the control word bit encoding and possible values are described in table 9. table 9. master station control word functions slave stations transmit the following status messages in the homepna header control word of all outgoing frames: 1. version_status: the homepna phy version of the slave station. the receiving station must revert to this version to interpret the packet. 2. power_status: the transmit power level of the transmitting slave station for the current frame. all homepna units support both low_power and high_power modes of operation. 3. speed_status: the transmit speed of the slave station for the current frame. receiving stations will adjust their receiver parameters to correctly interpret this frame. the slave control word bit encoding is identical to the master control word format. 1 mbps homepna phy loopback the homepna phy is capable of supporting internal loopback only. internal loopback in internal loopback, the transmitted data is returned to the receive data bus without transmitting data on the network. the mac must be programmed to support full-duplex operation and is responsible for comparing the transmitted data to that received. internal loopback is accomplished by setting the ? enable loopback mode ? in hpr0, bit 14, to 1. any1home link detection while consuming minimal network resources, amd ? s innovative any1home link detection packet provides a means to indicate to the mac, and thus the upper lay- ers of the system protocol, that a valid network (as de- fined by homepna) has been detected. the link detection packet is also capable of detecting a network failure and allows the upper layer protocol to take cor- rective action. thus, the any1home packet provides link indication that the mac requires for compliance to the microsoft pc98, pc99, and homepna revision 1.1 requirements without utilizing resources from the upper layers of the system protocol aid bit no. command function 5 lsb 0 = version 0 5msb 0 = set to low-power transmit mode. 1 = set to high-power transmit mode. 6lsb 0 = set to low-speed transmit mode. 1 = set to high-speed transmit mode. 6msbreserved
38 AM79C901A preliminary the any1home link packet consists of valid aid and pcom fields followed by four bytes of data. the receiv- ing node ? s mac will interpret this packet as a runt frame and will not forward the frame to upper layers, thus en- suring that no system resources are required. the AM79C901A homephy will transmit the any1home link packet as a result of not transmitting a normal data packet within the last 400 ms time period. similarly, the homephy will determine that it is not connected to a valid network (a link down state) after not receiving any data or link packets for a period greater than four seconds. the any1home link detec- tion status is reported via the led_link output pin and in the homepna phy status register (hpr1, bit 2). see table 18. 10base-t phy the 10base-t transceiver incorporates the physical layer function, including both clock recovery (endec) and transceiver function. data transmission over the 10base-t medium requires an integrated 10base-t mau. the transceiver meets the electrical require- ments for 10base-t as specified in ieee 802.3i. the transmit signal is filtered on the transceiver to reduce harmonic content per ieee 802.3i. since filtering is performed in silicon, external filtering modules are not needed. the 10base-t phy transceiver receives 10 mbps data from the mac across the mii at 2.5 million nibbles per second (parallel), or 10 million bits per sec- ond (serial) for 10base-t. it then manchester encodes the data before transmission to the network. the 10base-t block consists of the following sub-blocks: ? transmit process ? receive process ? interface status ? collision detect function ? jabber function ? reverse polarity detect refer to figure 22 for the 10base-t block diagram. figure 22. 10base-t transmit and receive data paths twisted pair transmit function data transmission over the 10base-t medium re- quires use of the integrated 10base-t mau and uses the differential driver circuitry on the tx pins. tx is a differential twisted-pair driver. when properly terminated, tx will meet the transmitter electrical re- quirements for 10base-t transmitters as specified in ieee 802.3, section 14.3.1.2. the load is a twisted pair cable that meets ieee 802.3, section 14.4. twisted pair receive function the rx+ port is a differential twisted-pair receiver. when properly terminated, the rx+ port will meet the electrical requirements for 10base-t receivers as specified in ieee 802.3, section 14.3.1.3. the receiver has internal filtering and does not require external filter modules or common mode chokes. signals appearing at the rx differential input pair are routed to the internal decoder. the receiver function meets the propagation delays and jitter requirements specified by the 10base-t standard. the receiver squelch level drops to half its threshold value after un- squelch to allow reception of minimum amplitude sig- nals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions. clock data manchester encoder clock data manchester decoder squelch circuit rx driver rx tx tx driver 22304b-24
AM79C901A 39 preliminary twisted pair interface status the AM79C901A device will power up in the link fail state. the auto-negotiation algorithm will apply to allow it to enter the link pass state. in the link pass state, receive activity which passes the pulse width/amplitude requirements of the rx inputs will cause the pcs control block to assert the carrier sense (crs) signal at the mii interface. a collision would cause the pcs control block to assert carrier sense (crs) and collision (col) signals at the mii. in the link fail state, this block would cause the pcs control block to deassert carrier sense (crs) and collision (col). in jabber detect mode, this block would cause the pcs control block to assert the col signal at the mii and allow the pcs control block to assert or deassert the crs pin to indicate the current state of the rx pair. if there is no receive activity on rx, this block would cause the pcs control block to assert only the col pin at the mii. if there is rx activity, this block would cause the pcs control block to assert both col and crs at the mii. collision detect function simultaneous activity (presence of valid data signals) from both the internal encoder transmit function and the twisted pair rx pins constitutes a collision, thereby causing the pcs control block to assert the col pin at the mii. jabber function the jabber function inhibits the 10base-t twisted pair transmit function of the AM79C901A device if the tx circuits are active for an excessive period (20-150 ms). this prevents one port from disrupting the network due to a stuck-on or faulty transmitter condition. if the max- imum transmit time is exceeded, the data path through the 10base-t transmitter circuitry is disabled (al- though link test pulses will continue to be sent). the pcs control block also asserts the col signal at the mii and sets the jabber detect bit in register 1 of the active phy. once the internal transmit data stream from the mendec stops, an unjab time of 250-750 ms will elapse before this block causes the pcs control block to deassert the col indication and re-enable the transmit circuitry. when jabber is detected, this block will cause the pcs control block to assert the col signal and allow the pcs control block to assert or deassert the crs signal to indicate the current state of the rx pair. if there is no receive activity on rx, this block causes the pcs control block to assert only the col signal at the mii. if there is rx activity, this block will cause the pcs control block to assert both col and crs on the mii. reverse polarity detect the polarity for 10base-t signals is set by reception of normal link pulses (nlp) or packets. polarity is locked, however, by incoming packets only. the first nlp received when trying to bring the link up will be ignored, but it will set the polarity to the correct state. the reception of two consecutive packets will cause the polarity to be locked, based on the polarity of the end of transmit data (etd). in order to change the polarity once it has been locked, the link must be brought down and back up again. auto-negotiation the object of the auto-negotiation function is to de- termine the abilities of the devices sharing a link. after exchanging abilities, the AM79C901A device and remote link partner device acknowledge each other and make a choice of which advertised abilities to support. the auto-negotiation function facilitates an ordered resolution between exchanged abilities. this exchange allows both devices at either end of the link to take maximum advantage of their respec- tive shared abilities. the auto-negotiation algorithm uses a burst of link pulses called fast link pulses (flps). the burst of link pulses are spaced between 55 and 140 s so as to be ignored by the standard 10base-t algorithm. the flp burst conveys information about the abilities of the sending device. the receiver can accept and decode an flp burst to learn the abilities of the sending device. the link pulses transmitted conform to the standard 10base-t template. the device can perform auto-ne- gotiation with reverse polarity link pulses. the AM79C901A device uses the auto-negotiation al- gorithm to select the type connection to be established according to the following priority: 10base-t full du- plex, then 10base-t half-duplex. see table 10. the auto-negotiation algorithm is initiated by the fol- lowing events: auto-negotiation enable bit is set, hard- ware reset, soft reset, transition to link fail state (when auto-negotiation enable bit is set), or auto-negotiation restart bit is set. the result of the auto-negotiation pro- cess can be read from the status register (summary status register, tbr24). by default, the link partner must be at least 10base-t half-duplex capable. the AM79C901A phy can auto- matically negotiate with the network and yield the high- est performance possible without software support. table 10. auto-negotiation capabilities network speed physical network type 20 mbps 10base-t, full duplex 10 mbps 10base-t, half duplex
40 AM79C901A preliminary auto-negotiation goes further by providing a mes- sage-based communication scheme called next pages before connecting to the link partner. soft reset function the phy control register (tbr0) incorporates the soft reset function (bit 15). it is a read/write register and is self-clearing. writing a 1 to this bit causes a soft reset. when read, the register returns a 1 if the soft reset is still being performed; otherwise, it is cleared to zero. note that the register can be polled to verify that the soft reset has terminated . under normal operating con- ditions, soft reset will be finished in 150 clock cycles. soft reset only resets the 10base-t phy unit registers to default values (some register bits retain their previ- ous values). soft reset does not reset the management interface. 10base-t loopback the 10base-t phy is capable of supporting two dif- ferent types of loopback, referred to as internal and external loopback. internal loopback in internal loopback, the transmitted data is returned to the receive data bus without transmitted data appear- ing on the network. the mac must be programmed to support full-duplex operation and is responsible for comparing the transmitted data to that received. inter- nal loopback is accomplished by setting the ? enable loopback mode ? in tbr0, bit 14, to 1. external loopback external loopback is accomplished by the use of an ex- ternal shorting plug. in this environment, the 10base-t phy is left in through mode (i.e., enable loopback mode in tbr0 = 0), the mac in full duplex. the transmitted data will then be looped back at the shorting plug into the receive circuitry and driven onto the receive data bus for the mac to process and verify. led support the controller can support up to five leds. led out- puts led_col , led_activity , led_link , led_speed , and led_power allow for direct con- nection of an led and its supporting pull-up device. the outputs are stretched to allow the human eye to recognize even short events that last only several mi- croseconds. the five led outputs are configured as shown in table 11. table 11. led default configuration ieee 1149.1 (jtag) test access port interface an ieee 1149.1-compatible boundary scan test ac- cess port is provided for board-level continuity test and diagnostics. all digital input, output, and input/output pins are tested. the following paragraphs summarize the ieee 1149.1-compatible test functions imple- mented in the controller. refer to the ieee 1149.1 boundary scan architecture document for details. boundary scan circuit the boundary scan test circuit requires four pins (tck, tms, tdi, and tdo), defined as the test access port (tap). it includes a finite state machine (fsm), an in- struction register, a data register array, and a power-on reset circuit. internal pull-up resistors are provided for the tdi, tck, and tms pins. tap finite state machine the tap engine is a 16-state fsm driven by the test clock (tck) and the test mode select (tms) pins. an independent power-on reset circuit is provided to en- sure that the fsm is in the test_logic_reset state at power-up. therefore, the trst is not provided. the fsm is also reset when tms and tdi are high for five tck periods. supported instructions in addition to the minimum ieee 1149.1 requirements (bypass, extest, and sample instructions), two additional instructions (idcode and tri_st) are provided to further ease board-level testing. all unused instruction codes are reserved. see table 12 for a sum- mary of supported instructions. led output indication driver mode pulse stretch led_col collision open drain - active low enabled led_activity activity open drain - active low enabled led_link link open drain - active low not applicable led_speed speed open drain - active low not applicable led_power power open drain - active low not applicable
AM79C901A 41 preliminary instruction register and decoding logic after the tap fsm is reset, the idcode instruction is always invoked. the decoding logic gives signals to con- trol the data flow in the data registers according to the current instruction. boundary scan register each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage, respectively. there are four possible operation modes in the bsr cell shown in table 13. other data registers other data registers are the following: 1. bypass register (1 bit) 2. device id register (32 bits) (table 14). boundary scan cells in boundary scan, most of the chip input and output latches are linked together to form a scan chain. the main purpose of this is board-level testing. see table 15. to force the output pins, use sample to load the bsr cells via the tdi pin and extest to force the output. program the output cells, and set the control cells to enable the output, or clear the control cells to float the output. to sample the chip inputs and outputs, use a sample command and cell values are shifted out through the tdo pin. check the values in the input cells. both input and output pins have input-type cells. table 15. boundary scan ring order table 12. ieee 1149.1 supported instruction summary instruction name instruction code description mode selected data register extest 0000 external test te s t bsr idcode 0001 id code inspection normal id reg sample 0010 sample boundary normal bsr tri_st 0011 force tri- state normal bypass bypass 1111 bypass scan normal bypass tri_st 0011 force tri- state normal bypass bypass 1111 bypass scan normal bypass table 13. bsr mode of operation 1 capture 2 shift 3 update 4 system function table 14. device id register bits 31-28 version bits 27-12 part number (1001 0000 0001 0000) bits 11-1 manufacturer id. the 11-bit manufacturer id code for amd is 00000000001 in accordance with jedec publication 106-a. bit 0 always a logic 1 bsr cell no. cell name cell type 1 pin no. 53 xtal_sel_l in 39 52 crs in 32 51 crs out 32 50 crs_col_oen co ? 49 col in 30 48 col out 30 47 txd3_csn in 28 46 txd2 in 27 45 txd1_sdi in 25 44 txd0_txdat in 24 43 tx_en in 23 42 tx_clk_oen co ? 41 tx_clk in 22 40 tx_clk out 22 39 gm_mode in 21 38 rx_er in 19 37 rx_er out 19 36 phy_sel in 17 35 rx_clk in 15 34 rx_clk out 15 33 rx_dv_rxen in 13 32 rx_dv_rxen out 13 31 rxd_oen co ? 30 rxd0_rxdat in 11 29 rxd0_rxdat out 11 28 rxd1 in 10 27 rxd1 out 10 26 rxd2 in 9 25 rxd2 out 9 24 rxd3 in 8 23 rxd3 out 8 22 led_speed co 6 21 led_speed in 6 20 led_speed out 6 19 led_power co 5
42 AM79C901A preliminary notes: 1. in = input cells, samples the device inputs and internal outputs; out = output cells, drives the device outputs and internal inputs; and co = control cells, controls the output enable. 2. bsr cell 0 is closest to tdo. 18 led_power in 5 17 led_power out 5 bsr cell no. cell name cell type 1 pin no. 16 led_activity co 3 15 led_activity in 3 14 led_activity out 3 13 led_col co 2 12 led_col in 2 11 led_col out 2 10 led_link co 1 9led_linkin1 8led_linkout1 7 mdc_sclk in 68 6mdioin66 5mdioout66 4 mdio_oen co ? 3isolatein65 2phy_adin64 1mode_miiin63 0 reset_l in 61 3. boundary register is 54 bits long. data path starts from tdi to cell 53, cell 0 to tdo.
AM79C901A 43 preliminary user accessible registers the AM79C901A phy has two types of user regis- ters: 1 mbps homepna phy management registers (hprs) and 10base-t phy management registers (tbrs). 1 mbps homepna phy management registers (hprs) the registers of the homepna phy are accessible via the mii or the spi interface. all reserved registers should not be written to, and reading them will return an undetermined value. table 16 lists all the registers implemented in the homepna phy. table 16. 1 mbps homepna phy management registers (hprs) register address symbol name basic/extended default value after h_reset 0 hpr0 control register b 0400h 1 hpr1 status register b 0841h 2 hpr2 phy_id register e 0000h 3 hpr3 phy_id register e 6b91h 4 hpr4 auto-negotiation register e 0021h 5 hpr5 auto-negotiation register e 0000h 6 hpr6 auto-negotiation register e 0000h 7 hpr7 auto-negotiation register e 0000h 8-15 hpr8-hpr15 reserved e ? 16 hpr16 phy control register e 0005h 17 hpr17 status/control register e 000xh 18 hpr18 phy txcomm register e 0000h 19 hpr19 phy txcomm register e 0000h 20 hpr20 phy rxcomm register e 0000h 21 hpr21 phy rxcomm register e 0000h 22 hpr22 phy aid register e 0000h 23 hpr23 phy noise control register e 03ffh 24 hpr24 phy noise control 2 register e f4xxh 25 hpr25 phy noise statistics register e 03ffh 26 hpr26 event status register e 0000h 27 hpr27 aid control register e 1440h 28 hpr28 isbi control register e 2c1ch 29 hpr29 tx control register e 0444h 30 hpr30 drive level control register e x549h 31 hpr31 analog control register e c000h
44 AM79C901A preliminary hpr0: homepna phy control register (register 0) table 17. hpr0: homepna phy control register (register 0) notes: 1. for collision test, the ?enable loopback mode? bit must also be set to ensure that collision traffic is not imposed on the network. 2. r/w = read/write; r = read only. bits name description read/ write default value (hex) 15 reset 1 = reset when read, 1= reset in process 0 = normal operation ** self clearing after ~70 s r/w 0 14 enable loopback mode 1 = loopback mode enable 0 = loopback mode disable r/w 0 13 speed selection 0 = 10 mbps r0 12 auto-negotiation enabled 1 = enabled 0 = disabled r0 11 power down 1 = power down 0 = normal operation (this bit is mirrored in phy control bit 4) r0 10 isolate 1 = electrically isolates phy from the mii/gpsi 0 = normal operation r/w 1 9 restart auto-negotiation 1 = restart auto-negotiation 0 = normal operation ** self clearing r0 8 duplex mode 1 = full-duplex (for loopback test only) 0 = half-duplex r/w 0 7 collision test (note 1) 1 = enable col test signal 0 = disable col test signal r/w 0 6:0 reserved write as 0, ignore on read r0
AM79C901A 45 preliminary hpr1: homepna phy status register (register 1) table 18. hpr1: homepna phy status register (register 1) bits name description read/write default value (hex) 15 100base-t4 0 = phy not able to perform 100base-t4 r0 14 100base-x full-duplex 0 = phy not able to perform full-duplex 100base-x r0 13 100base-x half-duplex 0 = phy not able to perform half-duplex 100base-x r0 12 10 mbps full-duplex 0 = phy not able to perform 10 mbps in full-duplex r0 11 10 mbps half-duplex 1 = phy able to perform 10 mbps in half-duplex r1 10:7 reserved reads will produce undefined results rx 6 management frame preamble suppression 1 = phy will accept management frames with preamble suppressed 0 = phy will not accept management frames with preamble suppressed r1 5 auto-negotiation complete 1 = auto-negotiation completed 0 = auto-negotiation not completed r0 4 remote fault 1 = remote fault detected 0 = normal operation r0 3 auto-negotiation ability 1 = phy is able to perform auto-negotiation 0 = phy is not able to perform auto-negotiation r0 2 link status 1 = link is up 0 = link is down this bit will be reset (latched low and re-enabled on read). r0 1 jabber detect 1 = jabber condition detected 0 = normal operation r0 0 extended capability 1 = extended register capability 0 = basic register set capability r1
46 AM79C901A preliminary hpr2 and hpr3: homepna phy id registers (registers 2 and 3) table 19. hpr2: homepna phy id register (register 2) table 20. hpr3: homepna phy id register (register 3) bits name description read/ write default value (hex) 15:0 phy_id msb (31-16) most significant bytes of the phy_id (bits 3-18) r0000 bits name description read/ write default value (hex) 15:10 phy_id lsb (15-10) ieee address (bits 19-24) r1a 9:4 phy_id lsb (9-4) manufacturer ? s model number r39 3:0 phy_id lsb (3-0) revision number r 1 (rev. a.1) 2 (rev. a.2) 3 (rev. a.3)
AM79C901A 47 preliminary hpr4: homepna phy auto-negotiation advertisement register (register 4) this register contains the advertised ability of the AM79C901A device. the purpose of this register is to advertise the technology ability to the link partner de- vice. when this register is modified, restart auto-ne- gotiation (register 0, bit 9) must be enabled to guarantee the change is implemented. table 21. hpr4: homepna phy auto-negotiation advertisement register (register 4) bits name description read/write default value (hex) 15 next page when set, the device wishes to engage in next page exchange. if cleared, the device does not wish to engage in next page exchange. r0 14 reserved r0 13 remote fault when set, a remote fault bit is inserted into the base link code word during the auto-negotiation process. when cleared, the base link code work will have the bit position for remote fault as cleared. r0 12:11 reserved r0 10 pause this bit should be set if the pause capability is to be advertised. r0 9 reserved r0 8 full-duplex 100base-tx this bit advertises full-duplex capability. when set, full-duplex capability is advertised. when cleared, full-duplex capability is not advertised. r0 7 half-duplex 100base-tx this bit advertises half-duplex capability for the auto-negotiation process. setting this bit advertises half-duplex capability. clearing this bit does not advertise half-duplex capability. r0 6 full-duplex 10base-t this bit advertises full-duplex capability. when set, full-duplex capability is advertised. when cleared, full-duplex capability is not advertised. r0 5 half-duplex 10base-t this bit advertises half-duplex capability for the auto-negotiation process. setting this bit advertises half-duplex capability. clearing this bit does not advertise half-duplex capability. r1 4:0 selector field the AM79C901A device is an ieee 802.3 compliant device. r01
48 AM79C901A preliminary hpr5: homepna phy auto-negotiation link partner ability register (register 5) the auto-negotiation link partner ability register is read only. the register contains the advertised ability of the link partner. the bit definitions represent the re- ceived link code word. this register contains either the base page or the link partner ? s next pages. the values contained in these registers are only valid once auto- negotiation has successfully completed, as indicated by bit 5 in hpr1, or if the next page exchange is used, after the page received (bit 1 of hpr6) has been set to logic one. table 22. hpr5: homepna phy auto-negotiation link partner ability register - base page format (register 5) table 23. hpr5: homepna phy auto-negotiation link partner ability register - next page format (register 5) bits name description read/write default value (hex) 15 next page link partner next page request r0 14 acknowledge link partner acknowledgment r0 13 remote fault link partner remote fault request r0 12:5 technology ability link partner technology ability field r0 4:0 selector field link partner selector field r0 bits name description read/write default value (hex) 15 next page link partner next page request r0 14 acknowledge link partner acknowledgment r0 13 message page link partner message page request r0 12 acknowledge 2 1 = link partner can comply with the request 0 = link partner cannot comply with the request r0 11 toggle link partner toggle bit r0 10:0 message field link partner ? s message code r0
AM79C901A 49 preliminary hpr6: homepna phy auto-negotiation expansion register (register 6) the auto-negotiation expansion register provides additional information that aids the auto-negotiation process. the auto-negotiation expansion register bits are read only. table 24. hpr6: homepna phy auto-negotiation expansion register (register 6) hpr7: homepna phy auto-negotiation next page register (register 7) the auto-negotiation next page register contains the next page link code word to be transmitted. on power-up the default value of 0x2001 represents a message page with the message code set to null. table 25. hpr7: homepna phy auto-negotiation next page register (register 7) reserved registers: hpr8 - hpr15 these registers should be ignored when read and should not be written to at any time. bits name description read/write default value (hex) 15:5 reserved r0 4 parallel detection fault 1 = parallel detection fault 0 = no parallel detection fault r0 3 link partner next page able 1 = link partner is next page able 0 = link partner is not next page able r0 2 next page able 1 = AM79C901A device channel is next page able 0 = AM79C901A device channel is not next page able r0 1 page received 1 = a new page has been received 0 = a new page has not been received r0 0 link partner auto- negotiation able 1 = link partner is auto-negotiation able 0 = link partner is not auto-negotiation able r0 bits name description read/write default value (hex) 15 next page AM79C901A device channel next page request r0 14 reserved r0 13 message page AM79C901A device channel message page request r0 12 acknowledge 2 1 = AM79C901A device channel can comply with the request 0 = AM79C901A device channel cannot comply with the request r0 11 toggle AM79C901A device channel toggle bit r0 10:0 message field message code field r000
50 AM79C901A preliminary hpr16: homepna phy control register (register 16) table 26. hpr16: homepna phy control register (register 16) note: writes to bits 1 and 2 will affect speed and power on node only. bits name description read/ write default value (hex) 15 remote command 1 = ignore remote commands 0 = normal operation r/w 0 14:13 reserved reads will produce undefined results. should be written as 0. r/w xx 12 sqe_test disable 1 = disables the sqe heartbeat which occurs after each transmission. 0 = the heartbeat assertion occurs on the col pin approximately 1-5 s after transmission and for a duration of 1 s. r/w 0 11 command low power 1 = command low power 0 = normal operation r/w 0 10 command high power 1 = command high power 0 = normal operation r/w 0 9 command low speed 1 = command low speed 0 = normal operation r/w 0 8 command high speed 1 = command high speed 0 = normal operation r/w 0 7 disable aid negotiation 1 = disable aid negotiation 0 = normal operation r/w 0 6 clear phy-event counter 1 = clear phy event counter 0 = normal operation **self clearing after ~100 ns r/w 0 5 disable squelch adaptation 1 = disable squelch adaptation 0 = normal operation r/w 0 4 power down 1 = power down 0 = normal operation (this bit is controlled by the hpr0, bit 11) r0 3 reserved reads will produce undefined results rx 2 high speed 1 = device is currently in high speed 0 = device is currently in low speed r/w 1 1 high power 1 = device is currently in high power 0 = device is currently in low power r/w 0 0 reserved reads will produce undefined results r/w x
AM79C901A 51 preliminary hpr17: homepna phy status/control register (register 17) the homepna phy status/control register pro- vides information regarding the global aspects of the operation of the phy. table 27. hpr17: homepna phy status/control register (register 17) hpr18 and hpr19: homepna phy txcomm registers (registers 18 and 19) table 28. hpr18 and hpr19: homepna phy txcomm registers (registers 18 and 19) the 32-bit transmitted data field is to be used for out- of-band communication between phy management entities. no protocol for out-of-band management has been defined. accessing the low word causes the phy to send all-0 pcoms until the high word has been ac- cessed. once accessed, the next transmitted packet will cause this register ? s contents to be shifted out in the pcom field of the transmitted packet. upon transmis- sion, this register will read back as all 0s. a non-null transmitted pcom will set the txpcom ready bit in the event status register (hpr26). an access to any of the two txpcom words will clear the txpcom ready bit in the istat register. bits name description read/write default value (hex) 15:13 reserved test control bits. reads will produce undefined results. should be written as 0. r00 12 any1home_ disable 1 = any1home link packet disabled 0 = any1home link packet enabled r/w 0 11:8 reserved test control bits. reads will produce undefined results. should be written as 0. r 3 7 reserved test control bit. reads will produce undefined results. should be written as 0. r0 6 received_power 1 = last packet received, was sent at high power 0 = last packet received, was sent at low power r0 5 received_speed 1 = last packet received, was sent at high speed 0 = last packet received, was sent at low speed r0 4 received_ver 1 = last packet received, was sent at version xx 0 = last packet received, was sent at version 0 r0 3:0 reserved test control bits. reads will produce undefined results. should be written as 0. rx bits name description read/write default value (hex) 15:0 phy_tx_comm (4) the 32-bit preamble transmitted on the homepna phy. hpr18 contains the high word and hpr19 the low word. r/w 0000
52 AM79C901A preliminary hpr20 and hpr21: homepna phy rxcomm registers (registers 20 and 21) table 29. hpr20 and hpr21: homepna phy rxcomm registers (registers 20 and 21) the 32-bit received data field to be used for out-of- band communication between phy management entities. no protocol for out-of-band management has been defined. accessing the low word of the register is sufficient to ensure that subsequently received packets will not overwrite the register contents. a non-null received pcom will set the rxpcom valid bit of the event status register (hpr26). accessing the high word of the register clears this bit and allows overwriting of the register by subsequent received packets. hpr22: homepna phy aid register (register 22) table 30. hpr22: homepna phy aid register (register 22) the phy ? s aid address is used for collision detec- tion. unless bit 7 of the control register is set, the phy is assured to select a unique aid address. addresses above efh are reserved. address ffh is defined to indicate a remote command. hpr23: homepna phy noise control register (register 23) table 31. hpr23: homepna phy noise control register (register 23) bits name description read/write default value (hex) 15:0 phy_rx_comm (4) the 32-bit preamble received by the homepna phy. hpr20 contains the high word and hpr21 the low word. r0000 bits name description read/write default value (hex) 15:8 phy_aid the access id of this phy. if phy_control disable aid negotiation is set, then writes to this bit will have no effect. r/w 00 7:0 noise events an 8-bit counter that records the number of noise events detected. overflows are held as ffh. can be cleared by setting bit 6 of hpr16. r/w 00 bits name description read/ write default value (hex) 15:8 noise floor if the input noise measurement (hpr25, bits 15:8) exceeds the peak measurement (hpr25, bits 7:0), this value is loaded into the noise level register hpr25, bits 15:8. r/w 03 7:0 noise ceiling if the input noise measurement (hpr25, bits 15:8) exceeds the peak measurement (hpr25, bits 7:0), this value is loaded into the noise level register hpr25, bits 7:0. r/w ff
AM79C901A 53 preliminary hpr24: homepna phy noise control 2 register (register 24) table 32. hpr24: homepna phy noise control 2 register (register 24) hpr25: homepna phy noise statistics register (register 25) table 33. hpr25: homepna phy noise statistics register (register 25) bits name description read/ write default value 15:8 noise attack sets the attack characteristics of the noise algorithm. high nibble sets number of noise events needed to raise the noise level immediately, while the low nibble is the number of noise events needed to raise the level at the end of an 870 ms period. r/w f4 7:0 reserved reads will produce undefined results. rxx bits name description read/ write default value (hex) 15:8 noise level this is the digital value of the slice_lvl_noise output. it is effectively a measure of the noise level on the wire and tracks noise by counting the number of false triggers of the noise comparator in an 800 ms window. when auto-adaptation is enabled (bit 5 of the phy_control register is false), this register is updated with the current noise count every 50 ns. when adaptation is disabled, this register may be written to and is used to generate both the slice_lvl_noise and slice_lvl_data signals. r/w 03 7:0 peak level this is a measurement of the peak level of the last valid (non-collision) aid received. r/w ff
54 AM79C901A preliminary hpr26: homepna phy event status register (register 26) table 34. hpr26: homepna phy event status register (register 26) hpr27: homepna phy aid control register (register 27) the homepna aid control register reports the state of each event source. any bit may be written and so facilitate software-stimulated event testing. table 35. hpr27: homepna phy aid control register (register 27) bits name description read/ write default value (hex) 15:10 reserved r0 9 rxpcom indicates a valid rxpcom. an access to the rxcom msb register 18 will clear this bit. r0 8 txpcom indicates a valid txpcom. any access to the txcom registers (registers 20 and 21) will clear this bit. r0 7:4 reserved reads will produce undefined results. should be written as 0. rx 3 packet received status is cleared by writing a 0. r/w 0 2 packet transmitted status is cleared by writing a 0. r/w 0 1 remote command received a valid remote command was received. status is cleared by writing a 0. r/w 0 0 remote command sent a remote command has been sent. status is cleared by writing a 0. r/w 0 bits name description read/ write default value (hex) 15:8 aid_interval this value defines the number of tclks (116.6 ns) separating aid symbols. r/w 14 7:0 aid_isbi this value defines the number of tclks (116.6 ns) separating aid symbol 0. r/w 40
AM79C901A 55 preliminary hpr28: homepna phy isbi control register (register 28) table 36. hpr28: homepna phy isbi control register (register 28) hpr29: homepna phy tx control register (register 29) table 37. hpr29: homepna phy tx control register (register 29) hpr30: homepna phy drive level control register (register 30) table 38. hpr30: homepna phy drive level control register (register 30) bits name description read/ write default value (hex) 15:8 isbi_slow this value defines the number of tclks (116.6 ns) separating data pulses for symbol 0 in low-speed mode. r/w 2c 7:0 isbi_fast this value defines the number of tclks (116.6 ns) separating data pulses for symbol 0 in high-speed mode. r/w 1c bits name description read/ write default value (hex) 15:8 tx_pulse_width this value defines the duration of a transmit pulse in osc cycles (16.7 ns). this will effectively determine the transmit spectrum of the phy. r/w 04 7:4 tx_pulse_cycles_n this value defines the number of pulses that will be driven onto the hrtxrx_n pin. r/w 4 3:0 tx_pulse_cycles_p this value defines the number of pulses that will be driven onto the hrtxrx_p pin. r/w 4 bits name description read/ write default value (hex) 15:12 reserved reserved. must be written as 0. read = x. rxx 11:6 high level control defines the drive level that will be utilized in the high power mode. r/w 15 5:0 low level control defines the drive level that will be utilized in the low power mode. r/w 09
56 AM79C901A preliminary hpr31: homepna phy analog control register (register 31) table 39. hpr31: homepna phy analog control register (register 31) 10base-t phy management registers (tbrs) the AM79C901A home networking device supports the mii basic register set and extended register set. both sets of registers are accessible through the mii management interface or via the spi interface. as specified in the ieee standard, the basic register set- status register (register 1). the extended register set consists of the control register (register 0) and the consists of registers 2 to 31 (decimal). table 40 lists all the 10base-t registers imple- mented in the device. all the reserved registers should not be written to, and reading them will return an undetermined value. table 40. 10base-t phy management registers (tbrs) bits name description read/ write default value (hex) 15:11 level_adjust global output slope adjustment. these bits control the number of current sources enabled for transmit. each bit represents a single current source. thus 10101 enables three current sources as does 11100. r/w 18 10:8 reserved reserved. must be written as 0. r/w 0 7 force_link_valid 1 = link status bit will be held valid 0 = normal operation r/w 0 6:0 reserved reserved. must be written as 0. r/w 0 register address symbol name basic/extended default value after h_reset 0 tbr0 phy control register b 1500h 1 tbr1 phy status register b 1xx9h 2 tbr2 phy identifier register e 0000h 3 tbr3 phy identifier register e 6b71h 4 tbr4 auto-negotiation advertisement register e 0061h 5 tbr5 auto-negotiation link partner ability register e 0000h 6 tbr6 auto-negotiation expansion register e 0004h 7 tbr7 auto-negotiation next page register e 2001h 8:15 tbr8-tbr15 reserved e ? 16 tbr16 status and enable register e 0000h 17 tbr17 phy control/status register e 0001h 18 tbr18 reserved e ? 19 tbr19 phy management extension register e ? 20:23 tbr20-tbr23 reserved e ? 24 tbr24 summary status register e 0000h 25:31 tbr25-tbr31 reserved e ?
AM79C901A 57 preliminary tbr0: 10base-t phy control register (register 0) table 41. tbr0: 10base-t phy control register (register 0) notes: 1. r/w = read/write, sc = self clearing, r = read only. 2. soft reset does not reset the pdx block. refer to the soft reset section for details. 3. bits 8 and 13 have no effect if auto-negotiation is enabled (bit 12 = 1). 4. if the isol pin of the chip and the isolate bit in register 0 is 1, this bit will be set. 5. the ? enable loopback mode ? bit must also be set to ensure that collision traffic is not imposed on the network. bits name description read/write (note 1) default va l u e (hex) 15 soft reset (note 2) when write 1 = phy software reset 0 = normal operation when read 1 = reset in process 0 = reset done r/w, sc 0 14 enable loopback mode 1 = loopback mode enable 0 = loopback mode disable r/w 0 13 speed selection (note 3) 1 = 1 0 0 m b p s ( n o t ava i l a bl e ) 0 = 10 mbps r0 12 auto-negotiation enable 1 = enable auto-negotiation 0 = disable auto-negotiation r/w 1 11 power down 1 = power down 0 = normal operation r/w 0 10 isolate (note 4) 1 = electrically isolates phy from the mii/gpsi 0 = normal operation r/w 1 9 restart auto-negotiation 1 = restart auto-negotiation 0 = normal operation r/w, sc 0 8 duplex mode (note 3) 1 = full-duplex 0 = half-duplex r/w 1 7 collision test (note 5) 1 = enable col signal test 0 = disable col signal test r/w 0 6:0 reserved write as 0, ignore on read r0
58 AM79C901A preliminary tbr1: 10base-t status register (register 1) the status register identifies the physical and auto- negotiation capabilities of the local phy. this register is read only; a write will have no effect. see table 42. table 42. tbr1: 10base-t phy status register (register 1) note: 1. lh = latching high, ll = latching low. bits name description read/write (note 1) default value (hex) 15 100base-t4 1 = 100base-t4 able 0 = not 100base-t4 able r0 14 100base-x full-duplex 1 = 100base-x full-duplex able 0 = not 100base-x full-duplex able r0 13 100base-x half-duplex 1 = 100base-x half-duplex able 0 = not 100base-x half-duplex able r0 12 10 mbps full-duplex 1 = 10 mbps full-duplex able 0 = not 10 mbps full-duplex able r1 11 10 mbps half-duplex 1 = 10 mbps half-duplex able 0 = not 10 mbps half-duplex able r1 10:7 reserved ignore when read rx 6 management frame preamble suppression 1 = phy can accept management (mgmt) frames with or without preamble 0 = phy can only accept mgmt frames with preamble r1 5 auto-negotiation complete 1 = auto-negotiation completed 0 = auto-negotiation not completed r0 4 remote fault 1 = remote fault detected 0 = no remote fault detected r , l h (note 1) 0 3 auto-negotiation ability 1 = phy able to auto-negotiate, 0 = phy not able to auto-negotiate r1 2 link status 1 = link is up 0 = link is down r , l l (note 1) 0 1 jabber detect 1 = jabber condition detected 0 = no jabber condition detected r0 0 extended capability 1 = extended register capabilities 0 = basic register set capabilities only r1
AM79C901A 59 preliminary tbr2 and tbr3: 10base-t phy identifier register (registers 2 and 3) registers 2 and 3 contain a unique phy identifier, con- sisting of 22 bits of the organizationally unique ieee identifier, a 6-bit manufacturer ? s model number, and a 4-bit manufacturer ? s revision number. the most signifi- cant bit of the phy identifier is bit 15 of register 2; the least significant bit of the phy identifier is bit 0 of reg- ister 3. register 2, bit 15, corresponds to bit 3 of the ieee identifier and register 2, bit 0, corresponds to bit 18 of the ieee identifier. register 3, bit 15, corre- sponds to bit 19 of the ieee identifier and register 3, bit 10, corresponds to bit 24 of the ieee identifier. regis- ter 3, bits 9-4, contain the manufacturer ? s model num- ber and bits 3-0 contain the manufacturer ? s revision number. these registers are shown in table 43 and table 44. table 43. tbr2: 10base-t phy identifier register (register 2) table 44. tbr3: 10base-t phy identifier register (register 3) bits name description read/ write default value (hex) 15:0 phy_id[31-16] ieee address (bits 3-18); register 2, bit 15 is msb of phy identifier r 0000 bits name description read/ write default value (hex) 15:10 phy_id[15-10] ieee address (bits 19-24) r1a 9:4 phy_id[9-4] manufacturer ? s model number (bits 5-0) r37 3:0 phy_id[3-0] revision number (bits 3-0); register 3, bit 0, is lsb of phy identifier r01
60 AM79C901A preliminary tbr4: 10base-t auto-negotiation advertisement register (register 4) this register contains the advertised ability of the AM79C901A home networking device. the purpose of this register is to advertise the technology ability to the link partner device. see table 45. when this register is modified, restart auto- negotiation (register 0, bit 9) must be enabled to guarantee the change is implemented. table 45. tbr4: 10base-t auto-negotiation advertisement register (register 4) bits name description read/ write default v a l u e (hex) 15 next page when set, the device wishes to engage in next page exchange. if cleared, the device does not wish to engage in next page exchange. r/w 0 14 reserved r0 13 remote fault when set, a remote fault bit is inserted into the base link code word during the auto-negotiation process. when cleared, the base link code work will have the bit position for remote fault as cleared. r/w 0 12:11 reserved r0 10 pause this bit should be set if the pause capability is to be advertised. r/w 0 9 reserved r0 8 full-duplex - 100base-tx this bit advertises full-duplex capability. when set, full-duplex capability is advertised. when cleared, full-duplex capability is not advertised. r0 7 half-duplex - 100base-tx this bit advertises half-duplex capability for the auto-negotiation process. setting this bit advertises half-duplex capability. clearing this bit does not advertise half-duplex capability. r0 6 full-duplex - 10base-t this bit advertises full-duplex capability. when set, full-duplex capability is advertised. when cleared, full-duplex capability is not advertised. r/w 1 5 half-duplex - 10base-t this bit advertises half-duplex capability for the auto-negotiation process. setting this bit advertises half-duplex capability. clearing this bit does not advertise half-duplex capability. r/w 1 4:0 selector field the 10base-t phy of the AM79C901A home networking device is an 802.3 compliant device. r01
AM79C901A 61 preliminary tbr5: 10base-t auto-negotiation link partner ability register (register 5) the auto-negotiation link partner ability register is read only. the register contains the advertised ability of the link partner. the bit definitions represent the re- ceived link code word. this register contains either the base page or the link partner ? s next pages. the values contained in these registers are only valid once auto- negotiation has successfully completed, as indicated by bit 5 in tbr1, or if the next page exchange is used after the page received (tbr6, bit 1) has been set to logic one. see table 46 and table 47. table 46. tbr5: 10base-t auto-negotiation link partner ability register (register 5) - base page format table 47. tbr5: 10base-t auto-negotiation link partner ability register (register 5) - next page format bits name description read/ write default value (hex) 15 next page link partner next page request r0 14 acknowledge link partner acknowledgment r0 13 remote fault link partner remote fault request r0 12:5 technology ability link partner technology ability field r0 4:0 selector field link partner selector field r0 bits name description read/ write default value (hex) 15 next page link partner next page request r0 14 acknowledge link partner acknowledgment r0 13 message page link partner message page request r0 12 acknowledge 2 1 = link partner can comply with the request 0 = link partner cannot comply with the request r0 11 toggle link partner toggle bit r0 10:0 message field link partner ? s message code r0
62 AM79C901A preliminary tbr6: 10base-t auto-negotiation expansion register (register 6) the auto-negotiation expansion register provides ad- ditional information which aids the auto-negotiation process. the auto-negotiation expansion register bits are read only. see table 48. table 48. tbr6: 10base-t auto-negotiation expansion register (register 6) tbr7: 10base-t auto-negotiation next page register (register 7) the auto-negotiation next page register contains the next page link code word to be transmitted. on power-up the default value of 2001h represents a message page with the message code set to null. see table 49. table 49. tbr7: 10base-t auto-negotiation next page register (register 7) reserved registers (registers 8-15, 18, 20-23, and 25-31) the AM79C901A device contains reserved registers at addresses 8-15, 18, 20-23, and 25-31. these registers should be ignored when read and should not be written to at any time. bits name description read/ write default value (hex) 15:5 reserved r0 4 parallel detection fault 1 = parallel detection fault 0 = no parallel detection fault r, lh 0 3 link partner next page able 1 = link partner is next page able 0 = link partner is not next page able r0 2 next page able 1 = AM79C901A device channel is next page able 0 = AM79C901A device channel is not next page able r1 1 page received 1 = a new page has been received 0 = a new page has not been received r, lh 0 0 link partner aneg able 1 = link partner is auto-negotiation able 0 = link partner is not auto-negotiation able r0 bits name description read/ write default value (hex) 15 next page AM79C901A device channel next page request r/w 0 14 reserved r0 13 message page AM79C901A device channel message page request r/w 1 12 acknowledge 2 1 = AM79C901A device channel can comply with the request 0 = AM79C901A device channel cannot comply with the request r/w 0 11 toggle AM79C901A device channel toggle bit r0 10:0 message field message code field r/w 001
AM79C901A 63 preliminary tbr16: 10base-t status and enable register (register 16) the status bits indicate when there is a change in the link status, duplex mode, auto-negotiation status, or speed status. register 16 contains the status and enable bits. the status is always updated whether or not the enable bits are set. when a status change oc- curs, the system will need to read this register to clear the status bits. see table 50. table 50. tbr16: 10base-t status and enable register (register 16) note: all bits, except bit 13, are cleared on read (cor). the register must be read twice to see if it has been cleared. bits name description read/ write default value (hex) 15:14 reserved r0 13 status test enable (note 1) 1 = when this bit is set, setting bits 12:9 of this register will cause a condition that will set bits 4:1 accordingly. the effect is to test the register bits with a forced interrupt condition. 0 = bits 4:1 are only set if the interrupt condition (if any bits in 12:9 are set) occurs. r/w 0 12 link status change enable 1 = link status change enable 0 = this interrupt is masked r/w 0 11 duplex mode change enable 1 = duplex mode change enable 0 = this interrupt is masked r/w 0 10 auto-negotiation change enable 1 = auto-negotiation change enable 0 = this interrupt is masked r/w 0 9 speed change enable 1 = speed change enable 0 = this interrupt is masked r/w 0 8 global enable 1= global interrupt enable 0 = this interrupt is masked r/w 0 7:5 reserved r0 4 link status change 1 = link status has changed on a port 0 = no change in link status r, lh 0 3 duplex mode change 1 = duplex mode has changed on a port 0 = no change in duplex mode r, lh 0 2 auto-negotiation change 1 = auto-negotiation status has changed on a port 0 = no change in auto-negotiation status r, lh 0 1 speed change 1 = speed status has changed on a port 0 = no change r, lh 0 0 global 1 = indicates a change in status of any of the above interrupts 0 = indicates no change in interrupt status r, lh 0
64 AM79C901A preliminary tbr17: 10base-t phy control/status register (register 17) this register is used to control the configuration of the 10 mbps phy of the AM79C901A home networking device. see table 1. table 1. tbr17: 10base-t phy control/status register (register 17) note: for these loopback paths, the data is also transmitted out of the mdi pins (tx). bits name description read/write default value (hex) 15:14 reserved r00 13 force link good enable 1 = link status forced to link up state 0 = link status is determined by the device r/w 0 12 disable link pulse 1 = link pulses sent from the 10base-t transmitter are suppressed 0 = link pulse enabled (normal operation) r/w 0 11 sqe_test disable 1 = disables the sqe heartbeat which occurs after each 10base-t transmission 0 = the heartbeat assertion occurs on the col pin approximately 1 s after transmission and for a duration of 1 s r/w 0 10 reserved r0 9 jabber detect disable 1 = disable jabber detect 0 = enable jabber detect r/w 0 8:7 reserved r00 6 receive polarity reversed 1 = receive polarity of the 10base-t receiver is reversed 0 = receive polarity is correct r0 5 auto receive polarity correction disable 1 = polarity correction circuit is disabled for 10base-t 0 = self correcting polarity circuit is enabled r/w 0 4 extended distance enable 1 = 10base-t receive squelch thresholds are reduced to allow reception of frames which are greater than 100 meters 0 = squelch thresholds are set for standard distance of 100 meters r/w 0 3 tx_disable 1 = tx outputs not active 0 = transmit valid data r/w 0 2 tx_crs_en 1 = crs is asserted when transmit or receive medium is active 0 = crs is asserted when receive medium is active r/w 0 1 reserved r0 0 phy isolated 1 = 10base-t phy is isolated 0 = 10base-t phy is enabled r1
AM79C901A 65 preliminary tbr19: 10base-t phy management extension register (register 19) table 2 contains the phy management extension reg- ister (register 19) bits. table 2. tbr19: 10base-t phy management extension register (register 19) tbr24: 10base-t summary status register (register 24) the summary status register is a global register con- taining status information. this register is read only and represents the most important data which a single register access can convey. the summary status regis- ter indicates the following: link status, full-duplex sta- tus, auto-negotiation alert, and speed. see table 3. table 3. tbr24: 10base-t summary status register (register 24) bits name description read/write default value (hex) 15:6 reserved write as 0; ignore on read r0 5 mgmt frame format 1 = last management frame was invalid (opcode error, etc.) 0 = last management frame was valid r0 4:0 phy address phy address defaults to 000x1 x = value on pin phy_add (i.e., 00001 or 00011) r 01/03 bits name description read/write default value (hex) 15:4 reserved write as 0; ignore on read r0 3link status 1 = link status is up 0 = link status is down r0 2 full-duplex 1 = operating in full-duplex mode 0 = operating in half-duplex mode r0 1 auto-negotiation alert 1 = auto-negotiation status has changed 0 = auto-negotiation status unchanged r0 0 speed 1 = operating at 100 mbps 0 = operating at 10 mbps r0
66 AM79C901A preliminary absolute maximum ratings storage temperature . . . . . . . . . . . . ? 65 c to +150 c ambient temperature (c). . . . . . . . . . -65 c to +70 c ambient temperature (i) . . . . . . . . . . -65 c to +85 c supply voltage with respect to v ss . . . . . . . . . . . . . ? 0.3 v to 3.63 v stresses above those listed under absolute maximum ratings may cause permanent device failure. function- ality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability . operating ranges commercial (c) devices temperature (ta) . . . . . . . . . . . . . . . . . .0 c to +70 c supply voltages (v dd ) . . . . . . . . . . . . . 3.0 v to 3.6 v all inputs within the range: . . . . . . v ss - 0.5 v to 5.5 v industrial (i) devices temperature (ta) . . . . . . . . . . . . . . . . -40 c to +85 c supply voltages (v dd ) . . . . . . . . . . . . . 3.0 v to 3.6 v all inputs within the range: . . . . . . v ss - 0.5 v to 5.5 v operating ranges define those limits between which the functionality of the device is guaranteed.
AM79C901A 67 preliminary dc characteristics notes: 1. v oh does not apply to open-drain output pins. 2. i oh2 applies to all other outputs. 3. i oz applies to all output and bidirectional pins. tests are performed at v in = 0 v and at v dd only. 4. i ix applies to all input pins except tdi, tclk, and tms pins. 5. i il and i ih apply to the tdi, tclk, and tms pins. 6. parameter not tested. value determined by characterization. 7. c clk applies only to the clk pin. 8. v out reflects output levels prior to 1: 2 transformer state. parameter symbol parameter description test conditions min max units digital i/o voltage v ih input high voltage 2.0 v v ih5v input high voltage (5v) 2.0 d vdd + 2.5 v v il input low voltage 0.8 v v ol output low voltage i ol1 = 4 ma i ol2 = 6 ma i ol3 = 12 ma 0.4 v v oh output high voltage (notes 1, 2) i oh1 = -4 ma i oh2 = -2 ma (note 2) 2.4 v v out output voltage on tx (peak) (note 8) 1.55 1.98 v v diff input differential squelch assert on rx (peak) 300 520 mv v diff input differential de-assert voltage on rx (peak) 150 300 mv digital i/o current i oz output leakage current (note 3) 0 v 68 AM79C901A preliminary switching waveforms key to switching waveforms switching test circuits figure 1. normal and tri-state outputs must be steady may change from h to l may change from l to h does not apply don ? t care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ? off ? state waveform inputs outputs ks000010-pal i oh i ol sense point v threshold c l 22304b-25
AM79C901A 69 preliminary ac characteristics gpsi 10base-t transmit timing (gpsi) note: not tested. figure 2. 10 mbps transmit timing (gpsi) no. symbol parameter description min max unit 1t s txdat, txen setup time to txclk edge 10 ? ns 2t h txdat, txen hold time from txclk edge 0 ? ns 3t pd transmit latency (txen sampled high to 1st bit of data) 240 360 ns 4t pd rxcrs assert from txen sampled high 0 130 ns 5t pd rxcrs de-assert from txen sampled low 0 130 ns 6t pwl txen de-assertion time between packets (note 1) 300 ? ns 1 2 3 4 5 6 txclk txen rxcrs tx txdat, txen end of packet start of packet 22304b-26
70 AM79C901A preliminary ac characteristics (continued) 10base-t receive timing (gpsi) figure 3. 10 mbps receive start of packet timing (gpsi) no. symbol parameter description min max unit 10 t pd cls assert latency from sop 200 300 ns 11 t pd rxcrs assert latency from sop 200 300 ns 12 t pd receive latency (sop to rxdat valid) 320 430 ns 13 t pd rxclk edge to rxdat transition ? 10 ns 14 t pd cls de-assert latency from eop 125 250 ns 15 t pd rxcrs de-assert latency from eop 165 255 ns 11 10 rxclk rx cls rxcrs rxdat start of packet 12 13 22304b-27
AM79C901A 71 preliminary ac characteristics (continued) 10base-t receive timing (gpsi) (continued) figure 4. 10 mbps receive end of packet timing (gpsi) 10base-t transmit clock timing (gpsi) 10base-t receive clock timing (gpsi) figure 5. 10 mbps transmit and receive clock timing (gpsi) 15 rxclk rx cls rxcrs end of packet 15 14 22304b-28 no. symbol parameter description min max unit 18 t per txclk period 99.99 100.01 ns 19 t pwh txclk pulse width high 45 55 ns 20 t pwl txclk pulse width low 45 55 ns no. symbol parameter description min max unit 18 t per rxclk period 99.99 100.01 ns 19 t pwh rxclk pulse width high 45 55 ns 20 t pwl rxclk pulse width low 45 55 ns txclk, rxclk 18 20 19 22304b-29
72 AM79C901A preliminary ac characteristics (continued) 1 mbps homepna transmit timing (gpsi) note: not tested. figure 6. 1 mbps homepna transmit timing (gpsi) no. symbol parameter description min max unit 23 t s txdat setup time to txclk 12 ? ns 24 t s txen setup time to txclk 10 ? ns 25 t h txdat hold time from txclk 10 ? ns 26 t h txen hold time from txclk 10 ? ns 27 t pd transmit latency (txen sampled high to sync pulse (5 mv)) 200 500 ns 28 t pd txen sampled high to cls active (note 1) ? 120 s 23 25 27 aid pcom sync 28 data txclk txdat txen hrtxrxp/n cls 24 26 22304b-30
AM79C901A 73 preliminary ac characteristics (continued) 1 mbps homepna receive timing (gpsi) note: not tested. figure 7. 1 mbps homepna receive timing (gpsi) no. symbol parameter description min max unit 29 t pd rxclk edge to rxdat transition (note 1) 010ns 30 t pd sync pulse detected to rxcrs clocked as active by mac (note 1) 650 850 ns 31 t pd last data pulse crosses noise slice level to rxcrs inactive (note 1) 15.98 16.10 s 32 t pd rxcrs inactive to cls inactive clocked into mac (note 1) ? 200 ns rxclk rxdat hrtxrxp/n rxcrs cls aid data data data sync 29 32 31 30 22304b-31
74 AM79C901A preliminary ac characteristics (continued) 1 mbps homepna clock timing (gpsi) note: during aid interval, rxclk and txclk stop for up to 140 s. figure 8. 1 mbps homepna clock timing (gpsi) no. symbol parameter description clock period unit idle (excluding ipg time) 35 t per txclk, rxclk period 583.3 ns 36 t pwh txclk, rxclk pulse width high 115.5 ns 37 t pwl txclk, rxclk pulse width low 467.8 ns preamble (first 64 bits of tx mac frame) 35 t per txclk, rxclk period 233.3 ns 36 t pwh txclk, rxclk pulse width high 115.5 ns 37 t pwl txclk, rxclk pulse width low 117.8 ns data (thoughtout the data phase) 35 t per txclk, rxclk period 233.3 ns - 10 s 36 t pwh txclk, rxclk pulse width high 115.5 ns 37 t pwl txclk, rxclk pulse width low 117.8 ns - 10 s ipg (96 bit times following crs falling edge) 35 t per txclk, rxclk period 233.3 ns 36 t pwh txclk, rxclk pulse width high 115.5 ns 37 t pwl txclk, rxclk pulse width low 117.8 ns txclk, rxclk 35 37 36 22304b-32
AM79C901A 75 preliminary ac characteristics (continued) mii 10base-t transmit timing (mii) note: not tested figure 9. 10 mbps transmit timing (mii) no. symbol parameter description min max unit 40 t s txd, tx_en setup time to txclk edge 10 ? ns 41 t h txd, tx_en hold time from txclk edge 0 ? ns 42 t pd transmit latency (tx_en sampled high to 1st bit of data) 240 360 ns 43 t pd crs assert from tx_en sampled high 0 430 ns 44 t pd crs de-assert from tx_en sampled low 0 430 ns 45 t pwl tx_en de-assertion time between packets (note 1) 1200 ? ns 40 41 42 43 44 45 tx_clk tx_en crs tx txd, tx_en end of packet start of packet 22304b-33
76 AM79C901A preliminary ac characteristics (continued) 10base-t receive timing (mii) note: rxd not tested. figure 10. 10 mbps receive start of packet timing (mii) no. symbol parameter description min max unit 48 t pd col assert latency from sop 200 300 ns 49 t pd crs assert latency from sop 200 300 ns 50 t pd receive latency (sop to rxd, rx_dv valid) (note 1) 625 1275 ns 51 t pd rx_clk edge to rxd, rx_dv transition ? 10 ns 52 t pd rx_dv de-assert latency eop 500 900 ns 53 t pd col de-assert latency from eop 100 700 ns 54 t pd crs de-assert latency from eop 500 900 ns 49 48 rx_clk rx col crs rxd, rx_dv start of packet 51 50 22304b-34
AM79C901A 77 preliminary ac characteristics (continued) 10base-t receive timing (mii) (continued) figure 11. 10 mbps receive end of packet timing (mii) 52 54 rx_clk rx col crs rx_dv end of packet 53 22304b-35
78 AM79C901A preliminary ac characteristics (continued) 10base-t transmit clock timing (mii) 10base-t receive clock timing (mii) figure 12. 10 mbps transmit and receive clock timing (mii) no. symbol parameter description min max unit 57 t per tx_clk period 399.6 400.4 ns 58 t pwh tx_clk pulse width high 180 220 ns 59 t pwl tx_clk pulse width low 180 220 ns no. symbol parameter description min max unit 57 t per rx_clk period 399.6 400.4 ns 58 t pwh rx_clk pulse width high 180 220 ns 59 t pwl rx_clk pulse width low 180 220 ns tx_clk, rx_clk 57 59 58 22304b-36
AM79C901A 79 preliminary ac characteristics (continued) 1 mbps homepna transmit timing (mii) note: not tested. figure 13. 1 mbps homepna transmit timing (mii) no. symbol parameter description min max unit 62 t s txd, tx_en setup time to tx_clk edge 10 ? ns 63 t h txd, tx_en hold time from tx_clk edge 10 ? ns 64 t pd transmit latency (tx_en sampled high to sync pulse (5 mv)) 200 500 ns 65 t pd tx_en sampled high to col active (note 1) ? 120 s 62 63 tx_clk txd, tx_en tx_en hrtxrxp/n col aid pcom sync 65 64 data 22304b-37
80 AM79C901A preliminary ac characteristics (continued) 1 mbps homepna receive timing (mii) note: not tested. figure 14. 1 mbps homepna receive timing (mii) no. symbol parameter description min max unit 68 t pd rx_clk edge to rxd, rx_dv transitions (note 1) 010ns 69 t pd sync pulse detected to crs clocked as active by mac (note 1) 650 850 ns 70 t pd last data pulse crosses data slice level to crs inactive (note 1) 15.98 16.10 s 71 t pd crs inactive to col inactive clocked into mac (note 1) ? 200 ns 22304b-38 rx_clk rxd, rx_dv hrtxrxp/n crs col aid data data data sync 68 71 70 69
AM79C901A 81 preliminary ac characteristics (continued) 1 mbps homepna clock timing (mii) note: during aid interval, rx_clk and tx_clk stop for up to 140 s. figure 15. 1 mbps homepna clock timing (mii) no. symbol parameter description clock period unit idle (excluding ipg time) 74 t per tx_clk, rx_clk period 2333.34 ns 75 t pwh tx_clk, rx_clk pulse width high 1165 ns 76 t pwl tx_clk, rx_clk pulse width low 1168 ns preamble (first 64 bits of tx mac frame) 74 t per tx_clk, rx_clk period 933.33 ns 75 t pwh tx_clk, rx_clk pulse width high 466 ns 76 t pwl tx_clk, rx_clk pulse width low 467 ns data (throughout the data phase) 74 t per tx_clk, rx_clk period 933 ns - 40 s 75 t pwh tx_clk, rx_clk pulse width high 466 ns - 40 s 76 t pwl tx_clk, rx_clk pulse width low 467 ns - 40 s ipg (96 bit times following crs falling edge) 74 t per tx_clk, rx_clk period 933.33 ns 75 t pwh tx_clk, rx_clk pulse width high 466 ns 76 t pwl tx_clk, rx_clk pulse width low 467 ns tx_clk, rx_clk 74 76 75 22304b-39
82 AM79C901A preliminary ac characteristics (continued) mdc/mdio figure 16. mii management timing no. symbol parameter description min max unit 79 t per mdc period 400 ? ns 80 t pwh mdc pulse width high 160 ? ns 81 t pwl mdc pulse width low 160 ? ns 82 t pd mdio output delay from mdc edge 0 300 ns 83 t s mdio input setup time to mdc edge 8 ? ns 84 t h mdio input hold time from mdc edge 8 ? ns 85 t z mdc to high impedance 540ns mdc mdio 79 84 83 82 85 81 80 22304b-40
AM79C901A 83 preliminary ac characteristics (continued) spi figure 17. spi timing no. parameter symbol parameter name min max unit 88 t pw sclk period 400 ? ns 89 t pwh sclk min pulse high 160 ? ns 90 t pwl sclk min pulse low 160 ? ns 91 t s cs setup to sclk 8 ? ns 92 t h cs hold to sclk 25 ? ns 93 t s sdi setup to sclk 8 ? ns 94 t h sdi hold to sclk 0 ? ns 95 t pd sclk to do valid 025ns 96 t pzd cs to do hi z ? 50 ns sclk cs sdi sdo 88 93 89 90 94 91 92 96 95 22304b-41
84 AM79C901A preliminary ac characteristics (continued) 10base-t pmd note: rx pulses narrower than t pwdrd (min) will maintain internal carrier sense on. rx pulses wider than t pwkrd (max) will turn internal carrier sense off. figure 18. 10 mbps transmit (tx) timing diagram figure 19. 10 mbps receive (rx) timing diagram no. symbol parameter description test conditions min max unit 99 t tetd transmit end of transmit data 250 375 ns 100 t pwkrd rx pulse width maintain/turn off threshold |v in | > |v ths | (note 1) 136 200 ns tx 99 22304b-42 rx v tsq+ v tsq- 100 100 100 22304b-43
AM79C901A 85 preliminary ac characteristics (continued) 1 mbps homepna analog notes: 1. all registers at default values and v cc = 3.3 v, 25 c. 2. measurements across hrtxtxp and hrtxtxn, differentially measured, with a 50 ? resistive load. figure 20. homepna phy ac waveform no. parameter symbol parameter name conditions typical units 103 t pw pulse width 133 ns 104 t pwh pulse width high 67 ns 105 t pwl pulse width low 67 ns 106 t vmaxp maximum voltage (positive) low power high power 1.00 2.00 v 107 t vmaxn maximum voltage (negative) low power high power 1.00 2.00 v 105 106 107 104 103 22304b-44
86 AM79C901A preliminary ac characteristics (continued) jtag note: 1. not tested; parameter guaranteed by design characterization. figure 21. jtag (ieee 1149.1) test signal timing no. parameter symbol parameter name min max unit 110 t per tck period 100 ? ns 111 t pwh tck high time 45 ? ns 112 t pwl tck low time 45 ? ns 113 t s tdi, tms setup time 8 ? ns 114 t h tdi, tms hold time 10 ? ns 115 t pd tdo valid delay 3 30 ns 116 t pd tdo float delay ? 50 ns tck tdi, tms tdo 110 116 111 112 113 115 110 110 114 22304b-45
AM79C901A 87 preliminary ac characteristics (concluded) external clock (xtal1) figure 22. external clock timing reset no. symbol parameter description min max unit 119 t per cycle time 16.665 16.669 ns 120 t pwh cycle high time 0.4 x t cycle 0.6 x t cycle ns 121 t pwl cycle low time 0.4 x t cycle 0.6 x t cycle ns xtal1 119 121 120 22304b-46 symbol parameter description min max unit t pw reset to reset 5000 ? ns
88 AM79C901A preliminary physical dimensions* pl 068 plastic leaded chip carrier (measured in inches) *for reference only. bsc is an ansi standard for basic space centering.
AM79C901A 89 preliminary physical dimensions* pqt 80 thin plastic quad flat pack (measured in millimeters) *for reference only. bsc is an ansi standard for basic space centering.
90 AM79C901A preliminary the contents of this document are provided in connection with advanced micro devices, inc. ( ? amd ? ) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, impli ed, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in am d ? s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpo se, or infringement of any intellectual property right. amd ? s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical im- plant into the body, or in other applications intended to support or sustain life, or in any other application in which the fai lure of amd ? s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks copyright ? 1999, 2000 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. alertit, any1home, eimr, eimr+, gigaphy, himib, homephy, imr2, mace, magic packet, netphy, pcnet, pcnet-home, quest, and quiet are trademarks of advanced micro devices, inc. rll25 is a trademark of tut systems, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. 22304c

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